ProStar325 Service Manual
78
Publication date 8 May 2003
JTAG output port
IrDA interface
Diagnostic functions
Serial ports, I/O RS232
The memory is addressed by the 18 address lines from the
Central Processing Unit (CPU). Additional “chip select” lines are
internally decoded in the microcontroller to address individual
blocks of memory. The input/output devices are provided by a
Field Programmable Gate Array (FPGA) and are memory-
mapped also.
The WR# and RD# lines are used to strobe data to and from the
addressed memory or I/O location.
FLASH memory occupies the top of the memory map and
contains a boot block, instrument firmware, and gateware for the
Xilinx FPGAs.
The boot block is written to the Flash memory using the JTAG
port (P1). Once installed, the other firmware is loaded via the
Ethernet TCP/IP interface.
4.3.1.2
Ethernet TCP/IP interface
Most of the functions of the Ethernet TCP/IP interface are
provided by an Ethernet Controller integrated circuit U12
operating at 33MHz. It contains all the necessary buffers and
handshake logic needed to correctly interface with this data
transmission protocol through the Microcontroller IC U1.
The microcontroller has a 3.3V PCI bus interface which is
compatible with the 3.3V I/O from the Ethernet Controller chip.
4.3.1.3
JTAG port
The Processor PWB is equipped with a JTAG accessible through
connector P5. It serially connects the Microcontroller CPU and
FPGA. This gives any device connected to the port access to all
the digital lines on these devices. It effectively makes a long
(hundreds of bits) serial shift register with one bit at each digital
line on the two devices. Values can be shifted into this register to
force levels on the device pins, and values can be read back from
the pins also.
The JTAG port loads the operating code into FLASH memory.
Any further updates of the operating code is done later through
the Ethernet interface. The JTAG port can also test RAM and
processor bus integrity without having the Microcontroller
running.
4.3.1.4
Field-Programmable Gate Array (FPGA)
The Processor PWB contains a FPGA Xilinx U11 which is used to
provide the I/O ports for the microcontroller and also to generate
some other logic timing required in the detector. This device has
the equivalent of 30,000 logic gates that can be configured and
connected as needed.
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