VersaLogic SPX-5, Reference Manual

Page 1: ...Reference Manual DOC REV 4 9 2013 SPX 5 Eight channel Solid State Switch Serial Peripheral Expansion SPX Board ...

Page 2: ...ocument is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 and the PC 104 logo are trademarks of t...

Page 3: ...sp contains additional information and resources for this product including Reference Manual PDF format Data sheets and manufacturers links for chips used in this product Utility routines and benchmark software This is a private page for SPX users that can be accessed only be entering this address directly It cannot be reached from the VersaLogic homepage ...

Page 4: ...ings 3 Electrostatic Discharge 3 Technical Support 4 Repair Service 4 Physical Details 5 SPX 5 Board Layout 5 Hardware Assembly 6 Connector Functions and Interface Cables 7 Jumper Summary 7 Connector Pinouts 8 Operation 9 Description 9 SPI Interface 9 Applications 10 Switch Control Code Example 11 Base Board SPI Registers 12 SPI Data Registers 14 ...

Page 5: ...ections on SPX boards are provided through screw terminal wire connections All SPX boards are RoHS compliant and industrial temperature rated ABOUT SPI The SPI bus specifies four logic signals SCLK Serial clock output from master MOSI Master output slave input output from master MISO Master input slave output output from slave and SS Slave select output from master The SPI implementation on VersaL...

Page 6: ...provides 500 mA total to be shared by all SPX modules External supply for switched loads 5 5VDC to 26 5VDC 1 5A External supply provided by the user High Side Low Side Switch 8 power MOSFET switches Loading All 8ch ON continuous 180mA per channel for 1 44A total load for device Single channel 550mA continuous Compatibility SPX EBX 11 Rev 6 and above compatible SPI controller 3 3V signaling SPI int...

Page 7: ...uropean Union EU beginning July 1 2006 VersaLogic Corporation is committed to supporting customers with high quality products and services meeting the European Union s RoHS directive Warnings ELECTROSTATIC DISCHARGE Electrostatic discharge ESD can damage boards disk drives and other components The circuit board must only be handled at an ESD workstation If an approved station is not available some...

Page 8: ... number The name of a technician or engineer that can be contact if any questions arise Quantity of items being returned The model and serial number barcode of each item A detailed description of the problem Steps you have taken to resolve or recreate the problem The return shipping address Warranty Repair All parts and labor charges are covered including return shipping charges for UPS Ground del...

Page 9: ...ensions of the SPX 5 board as well as the location of connectors jumpers and mounting holes Figure 1 SPX 5 Board Layout Not to scale All dimensions in inches 2 1 5 1 1 2 3 775 3 375 J1 SPX to Base Board J2 V1 1 0 39 0 55 0 8 0 125 DIA x4 Use 3mm or 4 standoffs 1 5 J3 1 5 J4 5 5 1 1 J6 J5 1 V2 ...

Page 10: ...r mounting holes These standoffs are secured to the board typically across the PC 104 and PC 104 Plus stack locations using pan head screws shown in Figure 2 Standoffs and screws are available as part number VL HDW 101 Figure 2 SPX Board Mounting Two SPX boards mounted across the PC 104 and PC 104 Plus stack locations ...

Page 11: ...e wires to 5 pin screw terminal 16 28 AWG wire J4 PWM Input Bare wires to 5 pin screw terminal 16 28 AWG wire J5 Switch 5 and 6 Bare wires to 5 pin screw terminal 16 28 AWG wire J6 Switch 7 and 8 Bare wires to 5 pin screw terminal 16 28 AWG wire Jumper Summary Table 2 Jumper Summary Jumper Block Description As Shipped V1 Slave Select 1 2 Slave Select 0 3 4 Slave Select 1 5 6 Slave Select 2 7 8 Sla...

Page 12: ...5_0 5 0V Table 4 J2 J6 Connector Pinouts Connector Pin Signal Name Description J2 1 D1 Switch 1 drain 2 S1 Switch 1 source 3 D2 Switch 2 drain 4 S2 Switch 2 source 5 GND Ground J3 1 D3 Switch 3 drain 2 S3 Switch 3 source 3 D4 Switch 4 drain 4 S4 Switch 4 source 5 GND Ground J4 1 PWM_IN1 PWM input 1 2 PWM_IN2 PWM input 2 3 NC Not connected 4 NC Not connected 5 GND Ground J5 1 D5 Switch 5 drain 2 S5...

Page 13: ...device will return to its previous state A fault register indicates when an error condition has occurred Note The switch can oscillate if subjected to continuous high loads and temperatures The MC33879 also incorporates internal voltage clamping of 45VDC and 20VDC for low and high side configurations respectively See the Freescale MC33879 Datasheet for more information SPI INTERFACE The MC33879 is...

Page 14: ...w of possible applications Figure 3 Simplified Application Diagram D1 D2 D3 D4 S1 S2 S3 S4 D5 D6 D7 D8 S5 S6 S7 S8 VDD VPWR EN DI SCLK CS DO IN5 IN6 GND 13 6V 3 3V Low Side Drive BAT V MOSI SCLK SSx MISO PWM1 PWM2 H Bridge Configuration High Side Drive M BAT V BAT V Freescale MC33879 ...

Page 15: ...OUT DX AL MOV DX 0x1D8 MOV AL 0x59 SPICONTROL SCLK idle low falling edge OUT DX AL 16bit frame manual SS0 asserted now Output MC33879 switch command MOV DX 0x1DC MOV AX 0xFF04 SPIDATA3 fault detect current ON all OUT DX AX SPIDATA2 MOSFET switch 3 ON CALL BUSY Poll BUSY flag to wait for SPI transaction Complete SPI transaction MOV DX 0x1D8 MOV AL 0x58 SPICONTROL De assert SS0 OUT DX AL Read Fault ...

Page 16: ...auto slave select modes SPILEN1 SPILEN0 Frame Length 0 0 8 bit 0 1 16 bit 1 0 24 bit 1 1 32 bit D3 MAN_SS SPI Manual Slave Select Mode This bit determines whether the slave select lines are controlled through the user software or are automatically controlled by a write operation to SPIDATA3 1DDh If MAN_SS 0 then the slave select operates automatically if MAN_SS 1 then the slave select line is cont...

Page 17: ...Hardware IRQ Enable Enables or disables the use of the selected IRQ IRQSEL by an SPI device 0 SPI IRQ disabled default 1 SPI IRQ enabled Note The selected IRQ is shared with PC 104 ISA bus devices CMOS settings must be configured for the desired ISA IRQ D2 LSBIT_1ST SPI Shift Direction Controls the SPI shift direction of the SPIDATA registers The direction can be shifted toward the least significa...

Page 18: ...ll initiate the SPI clock and if the MAN_SS bit 0 will also assert a slave select to begin an SPI bus transaction Increasing frame sizes from 8 bit use the lowest address for the least significant byte of the SPI data word for example the LSB of a 24 bit frame would be SPIDATA1 Data is sent according to the LSBIT_1ST setting When LSBIT_1ST 0 the MSbit of SPIDATA3 is sent first and received data wi...