Vertex Standard VXA-150, Service Manual

12

Circuit Description

TX/RX switch 

D1031

 (

MC2848

), then amplified by 

Q1043

(

2SC3356

) and 

Q1047

 (

2SK2973

), then applied to the

power amplifier 

Q1052

 which increases the signal level

up to 5 watts output power.

The transmit signal then passes through the antenna

switch 

D1037

 (

RLS135

), and is low-pass filtered to sup-

press away harmonic spurious radiation before delivery
to the antenna.

Automatic Transmit Power Control

RF power output from the final amplifier is sampled

by C1241/C1244 and is rectified by 

D1040

 (

HSM88WA

).

The resulting DC voltage passes through the Automatic
Power Controller 

Q1005

 (

NJM2902V

) to the APC attenu-

ator 

D1015

  (

RN739F

), and final amplifier 

Q1052

(

2SK2974

), so as to control the power output.

Transmit Inhibit

When the transmit PLL is unlocked, pin 7 of PLL chip

Q1032

 (

MB15A01PFV1

) goes to a logic low. The result-

ing DC “unlock” control voltage is switches off TX inhibit
switches 

Q1035

 (

2SA1602A

), 

Q1037

 (

UMW1

), and 

Q1041

(

DTA143EU

) to disable the supply voltage to transmitter

RF amplifier 

Q1043

, disabling the transmitter.

Spurious Suppression

Generation of spurious products by the transmitter is

minimized by the fundamental carrier frequency being
equal to the final transmitting frequency.  Additional har-
monic suppression is provided by a low-pass filter con-
sisting of L1024, L1026, & L1030 and C1242, C1245, C1247,
C1249, C1252, & C1257, resulting in more than 60 dB of
harmonic suppression prior to delivery of the RF signal
to the antenna.

PLL Frequency Synthesizer

PLL circuitry consists of VCO 

Q1023

 (

2SC5226

), VCO

buffer 

Q1029

 & 

Q1036

 (both 

2SC5226

), and PLL sub-

system IC 

Q1032

 (

MB15A01PFV1

), which contains a ref-

erence divider, serial-to-parallel data latch, programma-
ble divider, phase comparator and charge pump.

Stability is maintained by a regulated 3.5 V supply via

Q1030

 (

S-81235SGUP-DQI

) which feeds the PLL refer-

ence oscillator 

Q1045

 (

2SC4116GR

), as well as capacitors

associated with the 17.475 MHz frequency reference crys-
tal X1002.

In the receive mode, VCO 

Q1023

 oscillates between

143.4 and 172.4 MHz. The VCO output is buffered by

Q1029

 and 

Q1036

, and applied to the prescaler section of

Q1032

. There the VCO signal is divided by 64 or 65, ac-

cording to a control signal from the data latch section of

Q1032

, before being applied to the programmable divid-

er section of 

Q1032

. The data latch section of 

Q1032

 also

receives serial dividing data from the microprocessor

Q1014

 (

M38254M6

), which causes the pre-divided VCO

signal to be further divided in the programmable divider
section, depending upon the desired receive frequency,
so as to produce a 5 kHz derivative of the current VCO
frequency.

Meanwhile, the reference divider section of 

Q1032

 di-

vides the 17.475 MHz crystal reference from the reference
oscillator 

Q1045

 by 3495 to produce the 5 kHz loop refer-

ence. The 5 kHz signal from the programmable divider
(derived from the VCO) and that derived from the refer-
ence oscillator are applied to the phase detector section of

Q1032

, which produces a pulsed output with pulse dura-

tion depending on the phase difference between the in-
put signals. This pulse train is filtered to DC and returned
to the varactor 

D1015

 (

HVC350B

).

Changes in the level of the DC voltage applied to the

varactors affect the reactance in the tank circuit of the VCO,
changing the oscillating frequency of the VCO according
to the phase difference between the signals derived from
the VCO and the crystal reference oscillator. The VCO is
thus phase-locked to the crystal reference oscillator.

The output of the VCO 

Q1023

 is buffered by 

Q1029

before application to the 1st mixer, as described previous-
ly.

For transmission, the VCO 

Q1023

 oscillates between

118 and 137 MHz.  The remainder of the PLL circuitry is
shared with the receiver. However, the dividing data from
the microprocessor is such that the VCO frequency is at
the actual transmit frequency (rather than offset for IFs,
as in the receiving case).

Receive and transmit buses select which VCO is made

active by 

Q1021

 (

RT1N241M

). FET 

Q1042

 (

2SK880GR

)

buffers the VCV line for application to the tracking band-
pass filters in the receiver front end.

When the power saving feature is active, the micro-

processor periodically signals to the PLL IC 

Q1032

 to con-

serve power, and to shorten lock-up time.