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Plasma TV Service Manual

05/01/2006

Audio clock generation

• Generation of a field-locked audio master clock to support a constant number of audio clocks per
video field
• Generation of an audio serial and left/right (channel)

Digital I/O interfaces

• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status
information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)
• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-C

-C

– Output from decoder part, real-time and unscaled
– Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own
clock), or slave mode (external clock), with auxiliary timing and handshake signals
• Discontinuous data streams supported
• 32-word ´ 4-byte FIFO register for video output data
• 28-word ´ 4-byte FIFO register for decoded VBI-data output
• Scaled 4 :2 :2, 4 :1 :1, 4 :2 :0, 4 :1 :0 Y-C

-C

output

• Scaled 8-bit luminance only and raw CVBS data output
• Sliced, decoded VBI-data output.

Miscellaneous

• Power-on control
• 5 V tolerant digital inputs and I/O ports
• Software controlled power saving standby modes supported
• Programming via serial I 2 C-bus, full read back ability by an external controller, bit rate up to 400
kbits/s
• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”
• BGA156 package.

12.22.3. Pinning

SYMBOL PIN

TYPE

DESCRIPTION

XTOUT

crystal oscillator output signal; auxiliary signal

XTALO

24.576 MHz (32.11 MHz) crystal oscillator output; not
connected if TTL clock input of XTALI is used

SS(xtal)

ground for crystal oscillator

TDO

test data output for boundary scan test; note 2

XRDY

task flag or ready signal from scaler, controlled by XRQT

XCLK

I/O

clock I/O expansion port

XPD0

I/O

LSB of expansion port data

XPD2

I/O

MSB - 5 of expansion port data

XPD4

A10

I/O

MSB - 3 of expansion port data

XPD6

A11

I/O

MSB - 1 of expansion port data

TEST1

A12

I/pu

do not connect, reserved for future extensions and for testing:
scan input

TEST2

A13

I/pu

do not connect, reserved for future extensions and for testing:
scan input

AI41

analog input 41

TEST3

do not connect, reserved for future extensions and for testing

DD(xtal)

supply voltage for crystal oscillator

XTALI

input terminal for 24.576 MHz (32.11 MHz) crystal oscillator
or connection of external oscillator with TTL compatible
square wave clock signal

TDI

I/pu

test data input for boundary scan test; note 2

TCK

I/pu

test clock for boundary scan test; note 2

XDQ

I/O

data qualifier for expansion port

XPD1

I/O

MSB - 6 of expansion port data

XPD3

I/O

MSB - 4 of expansion port data

XPD5

B10

I/O

MSB - 2 of expansion port data

XTRI

B11

X-port output control signal, affects all X-port pins (XPD7 to
XPD0, XRH, XRV, XDQ and XCLK), enable and active
polarity is under software control (bits XPE in subaddress