VESTEL 17MB11, Service Manual

36 

Plasma TV Service Manual 

05/01/2006

12.29.2. Features 

• PC66-, PC100-, and PC133-compliant 
• Fully synchronous; all signals registered on positive edge of system clock 
• Internal pipelined operation; column address can be changed every clock cycle 
• Internal banks for hiding row access/precharge 
• Programmable burst lengths: 1, 2, 4, 8, or full page 
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes 
• Self Refresh Modes: standard and low power 
• 64ms, 4,096-cycle refresh 
• LVTTL-compatible inputs and outputs 
• 3.3V ±0.3V power supply 

12.29.3. Pin Descriptions 

PIN NUMBERS 

SYMBOL 

TYPE 

DESCRIPTION 

38  

CLK  

Input  

Clock:  CLK  is  driven  by the system clock. All SDRAM input 
signals are sampled on the positive edge of CLK. CLK also 
increments the internal burst counter and controls the output 
registers. 

37  

CKE 

Input 

Clock Enable: CKE activates (HIGH) and deactivates (LOW) 
the CLK signal. Deactivating the clock provides PRECHARGE 
POWER-DOWN and SELF REFRESH operation (all banks 
idle), ACTIVE POWER-DOWN (row active in any bank) or 
CLOCK SUSPEND operation (burst/access in progress). CKE 
is synchronous except after the device enters power-down and 
self refresh modes, where CKE becomes asynchronous until 
after exiting the same mode. The input buffers, including CLK, 
are disabled during power-down and self refresh modes, 
providing low standby power. CKE may be tied HIGH. 

19 

CS#  

Input 

Chip Select: CS# enables (registered LOW) and disables 
(registered HIGH) the command decoder. All commands are 
masked when CS# is registered HIGH. CS# provides for 
external bank selection on systems with multiple banks. CS# is 
considered part of the command code. 

16, 17, 18  

WE#,  CAS#, 
RAS#  

Input 

Command Inputs: WE#, CAS#, and RAS# (along with CS#) 
define the command being entered. 

39  

x4, x8: DQM 

15, 39  

x16:  DQML, 
DQMH 

Input 

Input/Output Mask: DQM is an input mask signal for write 
accesses and an output enable signal for read accesses. Input 
data is masked when DQM is sampled HIGH during a WRITE 
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQM is sampled HIGH during a READ 
cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is 
DQM. On the x16, DQML corresponds to DQ0-DQ7 and 
DQMH corresponds to DQ8-DQ15. DQML and DQMH are 
considered same state when referenced as DQM. 

20, 21

BA0, BA1 

Input 

Bank Address Inputs: BA0 and BA1 define to which bank the 
ACTIVE, READ, WRITE or PRECHARGE command is being 
applied. 

23-26, 29-34, 22, 
35 

A0-A11

Input 

Address Inputs: A0-A11 are sampled during the ACTIVE 
command (row-address A0-A11) and READ/WRITE command 
(column-address A0-A9 [x4]; A0-A8 [x8]; A0-A7 [x16]; with A10 
defining auto precharge) to select one location out of the 
memory array in the respective bank. A10 is sampled during a 
PRECHARGE command to determine if all banks are to be 
precharged (A10[HIGH]) or bank selected by BA0, BA1 
(A1[LOW]). The address inputs also provide the op-code 
during a LOAD MODE REGISTER command. 

2, 4, 5, 7, 8, 10, 
11, 13, 42, 44, 45, 
47, 48, 50, 51, 53

DQ0-DQ15

x16: I/O 

Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, 
and 51 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 
51, and 53 are NCs for x4). 

2, 5, 8, 11, 44, 47, 
50, 53

DQ0-DQ7

 x8: 

I/O Data 

Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for 

x4). 

5, 11, 44, 50 

DQ0-DQ3 

x4: I/O 

Data Input/Output: Data bus for x4. 

40  

NC  

–  

No Connect: These pins should be left unconnected.