I/O modules • 111
Counter modules 750-404/000-003
Modular I/O System
ETHERNET TCP/IP
Functional description
The counter module acquires the time between one or more rising edges of the
CLOCK input signal and calculates the frequency of the applied signal.
The calculation and process image update are initiated every 1
st
, every 4
th
or
every 16
th
rising edge depending on the integration time selected via the
CONTROL byte. The first detection of a rising edge starts the cyclic period
measurement and cannot provide a valid frequency value. In this case the mo-
dule will send 0xFFFFFFFF
H
for input information. The same input value is
returned when a static high or static low signal is applied to the CLOCK input.
If there are no signal changes seen at the CLOCK input, the module can be
forced to update the process image after defined parameterizable time spans. In
this state the module will send the non valid value 0xFFFFFFFF
H
too.
The following figures illustrate a process data cycle.
INPUT FREQ
DATA VALID
PROCESS DATA
TP
T1
0xFFFFFFFF
0xFFFFFFFF
D0..D3
D0..D3
D0..D3
D0..D3
D0..D3
T
P
= 1/f current period
T
1
Maximum data hold time (parameterizable)
Input Data
D0..D3
Timing diagram for process data update sequence
(Integration time = 1 period)
INPUT FREQ
DATA VALID
PROCESS DATA
4 TP
T1
T
P
= 1/f current period
T
1
Maximum data hold time (parameterizable)
Input Data
D0..D3
0xFFFFFFFF
D0..D3
0xFFFFFFFF
D0..D3
Timing diagram for process data update sequence
(integration time = 4 periods)