101019
OPERATIONS MANUAL PPM-LX800-G
3
The PPM-LX800-G board is based upon a 533 MHz AMD Geode™ LX800 and the
CS5536 companion chip. These devices incorporate the CPU, 128 KB of cache,
FPU, DDR SDRAM controller, Flash/ROM controller, an integrated display controller,
audio controller, PCI controller and the RTC/CMOS RAM.
Functional Capability
System Processor
Memory
The PPM-LX800-G can support a maximum of 1 GB of RAM with the SODIMM
socket located on the back of the board at
J107
.
Qualified SODIMMS are available directly from WinSystems.
The RAM can be user supplied, but must meet the following criteria:
200-Pin SODIMM PC2700 DDR SDRAM with gold fingers (up to 1 GB)
WinSystems cannot guarantee the operation of systems using nonqualified
SODIMM modules.
Installation is accomplished by inserting the module into the connector at
approximately a 30 degree angle. Press firmly to fully seat the module into the
connector and then press the module downward to snap it into the retaining
clamps.
Removal is accomplished by gently pulling outward on the retaining clamps until
the module springs up to the appropriate removal angle.
Interrupt Routing
Two 82C59A-compatible interrupt controllers accept inputs from the on-board
peripherals and the PC/104 Bus connectors. The configuration of interrupt inputs
is achieved in the BIOS CMOS setup discussed in the
later in
this manual.
Interrupt Status Register
One of the unique features of the PPM-LX800-G is the Interrupt Status Register
located at 1ECH. This read-only register allows all COM channels to share
interrupts and thus frees interrupts for other peripherals. If more than one COM
port is configured in the BIOS to use the same interrupt, the Interrupt Status
Register can be read to determine which port generates an interrupt. Once a
pending interrupt is serviced, the status register should be read again to see if
another interrupt is pending before exiting the routine.
Interrupt Status Register - 1ECH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
N/A
N/A
N/A
COM4
COM3
COM2
COM1
Note:
A
1
will be read for the device(s) with an interrupt pending.
WinSystems does not provide software support for implementing the
Interrupt Status Register to share interrupts. Some operating systems,
such as Windows XP and Linux, have support for sharing serial port
interrupts and examples are available. The user will need to implement
the appropriate software to share interrupts for the other devices.
