101019
OPERATIONS MANUAL PPM-LX800-G
12
POL0 - POL2 –
These registers are accessible when Page 1 is selected. They allow interrupt
polarity selection on a port–by–port and bit-by-bit basis. Writing a
1
to a bit position selects the
rising edge detection interrupts while writing a
0
to a bit position selects falling edge detection
interrupts.
ENAB0 - ENAB2
– These registers are accessible when Page 2 is selected. They allow for port-by-
port and bit-by-bit enabling of the edge detection interrupts. When set to a
1
the edge detection
interrupt is enabled for the corresponding port and bit. When cleared to
0
, the bit’s edge detection
interrupt is disabled. Note that this register can be used to individually clear a pending interrupt
by disabling and re-enabling the pending interrupt.
INT_ID0 – INT_ID2
– These registers are accessible when Page 3 is selected. They are used to
identify currently pending edge interrupts. A bit when read as a
1
indicates that an edge of the
polarity programmed into the corresponding polarity register has been recognized. Note that a
write to this register (value ignored) clears ALL of the pending interrupts in this register.
