WIZ127SR User’s Manual
36
4.5.
Hardware Flow Control Diagram (RS232 Level)
4.5.1.
CTS/RTS Mode Timing Diagram
Start
Check CTS
Send a byte
Is there
any data
to send?
End
No
Yes
It is fine to send
Do not send
8 bits Data
7 bits Data
9 bits Data
7 bits Data
7 bits Data
8 bits Data
9 bits Data
8 bits Data
9 bits Data
CTS
Tx
CTS
Tx
CTS
Tx
Send(CTS)
Figure 8. CTS signal Timing Diagram under CTS/RTS mode
Start
Check
Buffer
Set RTS to
HIGH
End
Buffer is free
Buffer will be
overflow
8 bits Data
7 bits Data
9 bits Data
7 bits Data
7 bits Data
8 bits Data
9 bits Data
8 bits Data
9 bits Data
RTS
Rx
RTS
Rx
RTS
Rx
Set RTS to
LOW
Receive and
store a byte
to buffer
Receive(RTS)
Figure 9. RTS signal Timing Diagram under CTS/RTS mode