![background image](http://html2.mh-extra.com/html/xess/xsv/xsv_manual_3294816030.webp)
29
Serial Port
The CPLD handles the interface to the serial port. The four active lines of the serial port
connect to general-purpose I/O pins on the CPLD as follows.
Serial Port
Pin
XC95108
CPLD Pin
RTS
82
TD
81
CTS
85
RD
80
Xchecker Cable
Header J21 provides an interface between the FPGA and an Xchecker cable. The
Xchecker cable can be used to perform configuration and readback operations on the
FPGA.
Xchecker Pin
Virtex FPGA Pin
1 – VCC (+5V)
N/A
2 – RT
132
3 – GND
N/A
4 – RD
133
6 – TRIG
139
7 – CCLK
179
9 – DONE
120
10 – TDI
167
11 – DIN
177
12 – TCK
239
13 – PROGRAM
122
14 – TMS
156
15 – INIT
123
XC95108
CPLD
rd
rts
td
cts
Serial Port
Connector
(J28)
level
shifters
Summary of Contents for XSV
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Page 34: ...33 B XSV Schematics The following pages show the detailed schematics for the XSV Board...
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Page 50: ...XSV Board V0 1 Layout...