Xilinx FMC XM101 LVDS QSE, User Manual

FMC XM101 User Guide

www.xilinx.com

19

UG538 (v1.1) September 24, 2010

XM101 Board Technical Description

PCA9543 Device Select Code as well as specific Device Code Select address when the 
XM101 is connected to a Xilinx board as defined in 

Table 1-1, page 7

.

The PCA9543 has a Control register which must be initialized by the IIC bus master to 
enable the channel 0 downstream IIC port. Channel 0 must be enabled prior to attempting 
to communicate with the two downstream programmable clock devices on the XM101.

After the IIC bus master enables PCA9543 channel 0 downstream IIC bus, the bus master 
can communicate directly with either Si570 component without further interaction with 
the Control register. The Control Register can be read by the IIC bus master. Table 11 
defines the PCA9543 Control Register. 

The two downstream IIC devices connected to the PCA9543 are at the same IIC address:

•

Si570 U1 IIC address is at 0x5D, PCA9543 control register bits CR[1:0] = 01

•

Si570 U2 IIC address is at 0x5D, PCA9543 control register bits CR[1:0] = 10

The U4 PCA9543 IIC bus switch to J1 FMC HPC connections are shown in 

Table 1-10

.

Table 1-8:

PCA9543 IIC Switch Device Select Code

Bit 7:4 Device 

Type Identifier 

Bit 3

Bit 2

Bit 1 

Bit 0 

LSB

Description

1110

0

GA0

GA1

Read/Write

Connected to mezzanine FMC 
HPC interface

Table 1-9:

PCA9543 Control Register

Bit 7:4

Bit 3:2

Bit 1

Bit 0

XXXX

XX

Channel 1 

Enable

(1)

Channel 0 

Enable

(2)

Notes: 

1. Channel 1 must be set to a logic 1 state by IIC bus master prior to attempting to 

communicate with the Si570 U2.

2. Channel 0 must be set to a logic 1 state by IIC bus master prior to attempting to 

communicate with the Si570 U1. 

Table 1-10:

IIC Bus Switch to J1 FMC HPC Connections

U4 PCA9543 IIC Bus Switch 

J1 FMC 

Connector

Net Name

Pin Number

Pin Number

SDA

U4.13

C31

SCL

U4.12

C30