HDMI 1.4/2.0 TX Subsystem
46
PG235 October 4, 2017
Chapter
3:
Designing with the Subsystem
For example, 1080p60, 12BPC, and 2PPC are used to show how all the clocks are derived.
Table
3
‐
3:
Clocking
HDMI Clocking
Clock
Function
Freq/Rate
Example
TMDS
clock
Source synchronous clock
to HDMI interface (This is
the actual clock on the
HDMI cable).
= 1/10 data rate
(for data rates < 3.4 Gb/s)
= 1/40 data rate
(for data rates > 3.4 Gb/s)
Data rate = 2.97 Gb/s
TMDS clock = 2.97/10 = 297 MHz
Data rate = 5.94 Gb/s
TMDS clock = 5.94/40 = 148.5 MHz
Data
clock
This is the actual data rate
clock. This clock is not used
in the system. It is only
listed to illustrate the clock
relations.
= TMDS clock
(for data rates < 3.4 Gb/s)
= TMDS clock * 4
(for data rates > 3.4 Gb/s)
Data rate = 2.97 Gb/s
Data clock = TMDS clock * 1 = 297 MHz
Data rate = 5.94 Gb/s
Data clock = TMDS clock * 4 = 594 MHz
TMDS clock = 148.5 MHz
Link
clock
Clock used for data
interface between HDMI
PHY Layer Module and
subsystem
= 1/4 of data clock
TMDS clock = 297 MHz
Data clock = 297 MHz
Link clock = 297 MHz/4 = 74.25 MHz
Data clock = 594 MHz
Link clock = 594 MHz/4 = 148.5 MHz
Pixel
clock
This is the internal pixel
clock. This clock is not used
in the system. It is only
listed to illustrate the clock
relations.
for 8 bpc pixel
clock = data clock
for 10 bpc pixel
clock = data clock/1.25
for 12 bpc pixel
clock = data clock/1.5
for 16 bpc pixel
clock = data clock/2
Video
clock
Clock used for video
interface
for dual pixel video
clock = pixel clock/2
for quad pixel video
clock = pixel clock/4
297 MHz/2 = 148.5 MHz for dual pixel
wide interface
297 MHz/4 = 74.25 MHz for quad pixel
wide interface
For more information on how to
choose the correct PLL in the targeted
devices, see the
Video PHY Controller
LogiCORE IP Product Guide
(PG230)
Notes:
1. The examples in the Example column are only for reference and do not cover all the possible resolutions. Each GT
has its own hardware requirements and limitations. Therefore, to use the HDMI 1.4/2.0 Transmitter Subsystem with
different GT devices, calculate the clock frequencies and make sure the targeted device is able to support it. When
using the HDMI 1.4/2.0 Transmitter Subsystem with Xilinx Video PHY Controller IP core, more information can be
found in
Video PHY Controller LogiCORE IP Product Guide
(PG230)
.