HDMI 1.4/2.0 TX Subsystem
56
PG235 October 4, 2017
Chapter
4:
Design Flow Steps
Output Generation
For details, see the
Vivado Design Suite User Guide: Designing with IP
(UG896)
FIFO Depth
C_ADDR_WIDTH
1024
32
32
1024
1024
2048
2048
4096
4096
8192
8192
Example Design
Design Topology
C_EXDES_TOPOLOGY
0
Pass-Through
0
Tx Only
1
TX PLL Type
C_EXDES_TX_PLL_SELECTION
0 (GTXE2)
6 (GTHE3/4)
CPLL
0
QPLL(GTXE2)
QPLL01(GTHE3/4)
3
6
RX PLL Type
C_EXDES_RX_PLL_SELECTION
3 (GTXE2)
0 (GTHE3/4)
CPLL
0
QPLL(GTXE2)
QPLL01(GTHE3/4)
3
6
Include NIDRU
C_EXDES_NIDRU
true
Include (Tick)
true
Exclude (Untick)
false
Table
4
‐
1:
Vivado IDE Parameter to User Parameter Relationship
(Cont’d)
Vivado IDE Parameter/Value
User Parameter/Value
Default Value