HDMI 1.4/2.0 TX Subsystem
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PG235 October 4, 2017
Chapter
5:
Example Design
This chapter covers the design considerations of a High-Definition Multimedia Interface
(HDMI™) 2.0 implementation using the performance features of these Xilinx® LogiCORE™
IPs:
• HDMI 1.4/2.0 with HDCP 1.4/2.2 Transmitter Subsystem
• HDMI 1.4/2.0 with HDCP 1.4/2.2 Receiver Subsystem (For Pass-through topology Only)
• Video PHY Controller
The design features the transmit-only and the pass-through operation modes for the HDMI
solution. In the transmit-only mode, the design displays a color bar pattern from the
LogiCORE IP Test Pattern Generator (TPG) core. In the pass-through mode, an external HDMI
source is used to send video data over the HDMI design. The reference design
demonstrates the use of the High-bandwidth Digital Content Protection System (HDCP)
Revision 1.4/2.2 capability of the HDMI solution. HDCP is used to securely send audiovisual
data from an HDCP protected transmitter to HDCP protected downstream receivers.
Typically, HDCP 2.2 is used to encrypt content at Ultra High Definition (UHD) while HDCP
1.4 is used as a legacy encryption scheme for lower resolutions.
The inrevium TB-FMCH-HDMI4K FMC daughter card is required for example designs
targeting the following boards:
• Kintex®-7 FPGA Evaluation Kit (KC705)
• Kintex® UltraScale™ FPGA Evaluation Kit (KCU105)
• Zynq®-7000 All Programmable SoC evaluation board (ZC706)
And it is not required while targeting the following boards, instead the on-board HDMI 2.0
circuitry is used.
• ZCU102 Evaluation Board
Hardware
The example design is built around the HDMI 1.4/2.0 Transmitter Subsystem (HDMI_TX_SS),
HDMI 1.4/2.0 Receiver Subsystem (HDMI_RX_SS) (Optional), Video PHY (VPHY) Controller
core and leverages existing Xilinx IP cores to form the complete system.
and
are illustrations of Overall HDMI Example Design block diagram while targeting
various Xilinx Evaluation Kits.