HDMI 1.4/2.0 TX Subsystem
63
PG235 October 4, 2017
Chapter
5:
Example Design
In pass-through mode, the VPHY Controller core recovers the high-speed serial video
stream, converts it to parallel data streams, forwards it to the HDMI_RX_SS core, which
extracts the video and audio streams from the HDMI stream and converts it to separate AXI
video and audio streams. The AXI video goes through the TPG core and the AXI audio goes
X-Ref Target - Figure 5-3
Figure
5
‐
3:
C705/KCU105/ZC706 HDMI Reference Design Clock and Datapath Diagram
X-Ref Target - Figure 5-4
Figure
5
‐
4:
ZCU102 HDMI Reference Design Clock and Datapath Diagram
KC705/KCU105/ZC706 Evaluation Kit
FPGA
TB-FMCH-HDMI4K
Clock Gen
(Si5324)
Oscillator
tx_gtrefclk clock p/n
nidru gtrefclk clock p/n
rx_gtrefclk clock p/n
rx_tmds_data(2:0)
txoutclk
tx_video_clk
tx_tmds_clk
HDMI TX
Subsystem
rxoutclk
rx_video_clk
Cable Driver
(DP159)
tx_tmds_clk_p/n
tx_tmds_data(2:0)
HDMI TX
HDMI RX
rx_tmds_clk_p/n
axis_tx_tmds_data_ch(2:0)
rx_tmds_clk
HDMI RX
Subsystem
axis_rx_tmds_data_ch(2:0)
Test
Pattern
Generator
Audio
Generator
OSC
Video PHY
Controller
TX
RX
axis_video
axis_audio
axis_video
axis_audio
reference clock in
pass-through mode
reference clock in
tx-only mode
ZCU102 Evaluation Kit
FPGA
HDMI 2.0 Circuitry
Clock Gen
(Si5324)
Oscillator
tx_gtrefclk clock p/n
nidru gtrefclk clock p/n
rx_gtrefclk clock p/n
rx_tmds_data(2:0)
txoutclk
tx_video_clk
tx_tmds_clk
HDMI TX
Subsystem
rxoutclk
rx_video_clk
Cable Driver
(DP159)
tx_tmds_clk_p/n
tx_tmds_data(2:0)
HDMI TX
HDMI RX
rx_tmds_clk_p/n
axis_tx_tmds_data_ch(2:0)
rx_tmds_clk
HDMI RX
Subsystem
axis_rx_tmds_data_ch(2:0)
Test
Pattern
Generator
Audio
Generator
OSC
Video PHY
Controller
TX
RX
axis_video
axis_audio
axis_video
axis_audio
reference clock in
pass-through mode
reference clock in
tx-only mode