HDMI 1.4/2.0 TX Subsystem
64
PG235 October 4, 2017
Chapter
5:
Example Design
through a customized audio generation block. The two AXI streams eventually reach the
HDMI_TX_SS core, which converts the AXI video and audio streams back to an HDMI stream
before being transmitted by the VPHY Controller core as a high-speed serial data stream.
The transition minimized differential signaling (TMDS) clock from the HDMI In interface is
forwarded to the HDMI TX transceiver via the SI53xx clock generator in the HDMI 2.0 FMC
card or on-board HDMI 2.0 circuitry.
In TX only mode, the colorbar pattern is generated by the TPG in form of AXI video stream
and the low frequency audio is generated by the customized audio processing block in form
of AXI audio stream. The two streams are forwarded to the HDMI_TX_SS for HDMI stream
conversion then to the VPHY for transmission.
High-level control of the system is provided by a simplified embedded processor
subsystem containing I/O peripherals and processor support IP. A clock generator block
and a processor system reset block supply clock and reset signals for the system,
respectively. See
and
for a block diagrams of the three types of
processor subsystems supported by HDMI Example Design flow.
X-Ref Target - Figure 5-5
Figure
5
‐
5:
HDMI Reference Design Block Diagram (MicroBlaze)
tpg_ss
audio_ss
microblaze_ss
MicroBlaze
Processor
Microblaze
Debug
Module
LMB bram
controller
Block RAM
Clock Wizard
Processor
System Reset
Module
AXI interconnect (AXI lite)
LMB bram
controller
LMB
LMB
LMB bram
controller
Block RAM
LMB bram
controller
Audio Pattern
Gen
AXI UART
(lite)
AXI INTC
AXI IIC
FPGA IO
FPGA IO
Clock Wizard
HDMI ACR
AXI GPIO
Test Pattern
Generator
HDMI
Transmitter
Subsystem
HDMI
Receiver
Subsystem
Video PHY
Controller