Xilinx Kintex-7 FPGA KC705, User Manual

Page 1: ...Kintex 7 FPGA KC724 GTX Transceiver Characterization Board User Guide UG932 v2 2 October 10 2014...

Page 2: ...subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe perf...

Page 3: ...tion 17 PROG_B Push Button 18 DONE LED 18 INIT LED 19 System ACE SD Controller 19 System ACE SD Controller Reset 19 System ACE SD Configuration Address DIP Switches 19 200 MHz 2 5V LVDS Oscillator 20...

Page 4: ...ization Board UG932 v2 2 October 10 2014 Solution Centers 63 References 63 Appendix E Regulatory and Compliance Information Declaration of Conformity 65 Directives 65 Standards 65 Electromagnetic Comp...

Page 5: ...ex 7 XC7K325T 3 FFG900E FPGA Onboard power supplies for all necessary voltages Terminal blocks for optional use of external power supplies Digilent USB JTAG programming port System ACE SD controller P...

Page 6: ...2 Module Interface GTX Transceivers QUAD 115 QUAD 116 QUAD 117 QUAD 118 Kintex 7 FPGA XC7K325T 3 FFG900E Select I O Termination and VTT Jacks Analog Digital Converter XADC FMC1 Interface High Performa...

Page 7: ...electrostatic discharge ESD Follow standard ESD prevention measures when handling the board Caution Do not remove the rubber feet from the board The feet provide clearance to prevent short circuits o...

Page 8: ...Active Heatsink Power Connector page 16 12 U1 Kintex 7 XC7K325T 3 FFG900E FPGA page 17 13 U8 USB JTAG configuration port Digilent module page 17 14 SW3 PROG_B Push Button page 18 15 DS21 DONE LED page...

Page 9: ...ut than J2 Connecting an ATX 6 pin connector into J2 will damage the KC724 board and void the board warranty Power can also be provided through Connector J131 which accepts an ATX hard disk 4 pin powe...

Page 10: ..._IO VCCBRAM VCCO_HR VCCO_HP Power Supply 12V PWR IN J2 or J5 or J131 Power Controller 1 UCD9248PFC U9 Switching Regulator 1 0V at 20A max U5 Switching Regulator 1 8V at 10A max U6 Switching Regulator...

Page 11: ...o 3 6V VCCBRAM 1 0V PTD08D210W VOUT B Adjustable switching regulator dual 10A 0 6Vto 3 6V VCCAUX_IO 1 8V UCD9248PFC U10 PMBus compliant digital PWM system controller Addr 53 PTD08D210W VOUT A U7 Adjus...

Page 12: ...upply capable of providing the required current Caution The SW10 power regulator enable switch callout 8 Figure 1 2 see Disabling Onboard Power must be set to the OFF position before turning ON the ma...

Page 13: ...and J155 respectively Default Jumper and Switch Positions A list of jumpers and switches and their required positions for normal board operation is provided in Appendix A Default Jumper and Switch Po...

Page 14: ...he three modules can be plugged into connectors J66 and J97 in the outlined and labeled power module location shown in Figure 1 6 Table 1 3 lists the nominal voltage values for the MGTAVCC MGTAVTT and...

Page 15: ...n The 7 series GTX Module MUST be removed when providing external power to the GTX transceiver rails Caution The GTX transceiver power terminal block J7 has a maximum load current contact rating of 24...

Page 16: ...nk Figure 1 8 is provided for the FPGA A 12V fan is affixed to the heatsink and is powered from the 3 pin friction lock header J121 Figure 1 9 The fan power connections are detailed in Table 1 4 X Ref...

Page 17: ...the following options USB JTAG configuration port Digilent module System ACE SD controller The FPGA is configured through the Digilent onboard USB to JTAG configuration logic module U8 where a host c...

Page 18: ...SW3 callout 14 Figure 1 2 grounds the active Low program pin of the FPGA DONE LED The DONE LED DS21 callout 15 Figure 1 2 indicates the state of the DONE pin of the FPGA When the DONE pin is High DS21...

Page 19: ...sing the SASD RESET push button SW7 callout 18 Figure 1 2 resets the System ACE SD controller The reset pin is an active Low input System ACE SD Configuration Address DIP Switches DIP switch SW8 shown...

Page 20: ...1 reset pin Table 1 8 shows the FPGA I O mapping for the SuperClock 2 module interface The KC724 board also supplies UTIL_5V0 UTIL_3V3 UTIL_2V5 and VCCO_HR input power to the clock module interface Ta...

Page 21: ...ontrol I O In Out LVCMOS18 CM_CTRL_8 77 NC G28 Control I O In Out LVCMOS18 CM_CTRL_9 79 LOL H25 Control I O Output LVCMOS18 CM_CTRL_10 81 INT_ALRM Input H24 Control I O Output LVCMOS18 CM_CTRL_11 83 C...

Page 22: ...Figure 1 2 Table 1 9 User LEDs FPGA U1 Schematic Net Name Reference Designator Pin Function Direction IOSTANDARD A20 User LED Output LVCMOS18 APP_LED1 DS19 A17 User LED Output LVCMOS18 APP_LED2 DS20 A...

Page 23: ...o all GTX transceiver and reference clock pins on the FPGA as shown in Figure 1 13 The GTX transceivers are grouped into four sets of four RX TX lanes Four lanes are referred to as a Quad Note Figure...

Page 24: ...ansceiver Characterization Board UG932 v2 2 October 10 2014 Chapter 1 KC724 Board Features and Operation X Ref Target Figure 1 13 Figure 1 13 GTX Quad Locations UG932_c1_13_062312 QUAD_116 QUAD_115 QU...

Page 25: ...Table 1 12 X Ref Target Figure 1 14 Figure 1 14 A GTX Connector Pad B GTX Connector Pinout Table 1 12 GTX Transceiver Pins U1 FPGA Pin Net Name Quad Connector Trace Length mils Y2 115_TX0_P 115 J83 2...

Page 26: ...2 357 P6 116_RX2_P 116 J84 2 218 P5 116_RX2_N 116 J84 2 218 L4 116_TX3_P 116 J84 2 555 L3 116_TX3_N 116 J84 2 555 M6 116_RX3_P 116 J84 2 821 M5 116_RX3_N 116 J84 2 821 K2 117_TX0_P 117 J85 2 617 K1 11...

Page 27: ...J86 2 787 B1 118_TX2_N 118 J86 2 789 B6 118_RX2_P 118 J86 2 681 B5 118_RX2_N 118 J86 2 680 A4 118_TX3_P 118 J86 3 044 A3 118_TX3_N 118 J86 3 044 A8 118_RX3_P 118 J86 3 515 A7 118_RX3_N 118 J86 3 515...

Page 28: ...FPGA and the CP2103 at U34 are listed in Table 1 15 J7 117_REFCLK1_N 117 J85 C8 118_REFCLK0_P 118 J86 C7 118_REFCLK0_N 118 J86 E8 118_REFCLK1_P 118 J86 E7 118_REFCLK1_N 118 J86 Table 1 13 GTX Transce...

Page 29: ...tion The FMC HPC connector is a 10 x 40 position socket See Appendix C VITA 57 1 FMC Connector Pinouts for a cross reference of signal names to pin coordinates FMC1 HPC connector provides connectivity...

Page 30: ...AF10 FMC1_CLK0_M2C_N H5 AD18 FMC1_CLK1_M2C_P G2 AE18 FMC1_CLK1_M2C_N G3 AF17 FMC1_HA00_CC_P F4 AG17 FMC1_HA00_CC_N F5 AF18 FMC1_HA01_CC_P E2 AG18 FMC1_HA01_CC_N E3 AK16 FMC1_HA02_P K7 AK15 FMC1_HA02_...

Page 31: ...AG5 FMC1_HB00_CC_N K26 AD4 FMC1_HB01_P J24 AD3 FMC1_HB01_N J25 AC2 FMC1_HB02_P F22 AC1 FMC1_HB02_N F23 AD2 FMC1_HB03_P E21 AD1 FMC1_HB03_N E22 AC5 FMC1_HB04_P F25 AC4 FMC1_HB04_N F26 AD6 FMC1_HB05_P E...

Page 32: ...1 FMC1_I2C_SCL C30 U39 8 1 FMC1_I2C_SDA C31 AD12 FMC1_LA00_CC_P G6 AD11 FMC1_LA00_CC_N G7 AE11 FMC1_LA01_CC_P D8 AF11 FMC1_LA01_CC_N D9 AA12 FMC1_LA02_P H7 AB12 FMC1_LA02_N H8 AA8 FMC1_LA03_P G9 AB8...

Page 33: ...N H20 AE13 FMC1_LA16_P G18 AF13 FMC1_LA16_N G19 AG10 FMC1_LA17_CC_P D20 AH10 FMC1_LA17_CC_N D21 AK14 FMC1_LA18_CC_P C22 AK13 FMC1_LA18_CC_N C23 AH14 FMC1_LA19_P H22 AJ14 FMC1_LA19_N H23 AJ13 FMC1_LA20...

Page 34: ...M2C_L H2 U23 8 1 FMC1_FMC2_TCK D29 U23 3 U19 1 1 FMC1_TDI D30 U23 6 1 FMC1_FMC2_TMS D33 Notes 1 This signal is not directly connected to the FPGA The value in the leftmost column represents the device...

Page 35: ...FMC2_HA06_P K10 AD24 FMC2_HA06_N K11 AD21 FMC2_HA07_P J9 AE21 FMC2_HA07_N J10 AG24 FMC2_HA08_P F10 AH24 FMC2_HA08_N F11 AJ24 FMC2_HA09_P E9 AK25 FMC2_HA09_N E10 AE25 FMC2_HA10_P K13 AF25 FMC2_HA10_N K...

Page 36: ...P J21 V24 FMC2_HA22_N J22 W21 FMC2_HA23_P K22 W22 FMC2_HA23_N K23 G13 FMC2_HB00_CC_P K25 F13 FMC2_HB00_CC_N K26 L16 FMC2_HB01_P J24 K16 FMC2_HB01_N J25 L15 FMC2_HB02_P F22 K15 FMC2_HB02_N F23 L12 FMC2...

Page 37: ...J33 C14 FMC2_HB15_N J34 B13 FMC2_HB16_P F34 A13 FMC2_HB16_N F35 D12 FMC2_HB17_CC_P K37 D13 FMC2_HB17_CC_N K38 C15 FMC2_HB18_P J36 B15 FMC2_HB18_N J37 B14 FMC2_HB19_P E33 A15 FMC2_HB19_N E34 M24 FMC2_H...

Page 38: ...2 H29 FMC2_LA08_N G13 J27 FMC2_LA09_P D14 J28 FMC2_LA09_N D15 L30 FMC2_LA10_P C14 K30 FMC2_LA10_N C15 K26 FMC2_LA11_P H16 J26 FMC2_LA11_N H17 M29 FMC2_LA12_P G15 M30 FMC2_LA12_N G16 N27 FMC2_LA13_P D1...

Page 39: ...G27 T30 FMC2_LA25_N G28 P26 FMC2_LA26_P D26 R26 FMC2_LA26_N D27 R28 FMC2_LA27_P C26 T28 FMC2_LA27_N C27 T26 FMC2_LA28_P H31 T27 FMC2_LA28_N H32 U29 FMC2_LA29_P G30 U30 FMC2_LA29_N G31 V26 FMC2_LA30_P...

Page 40: ...ways of setting the XADC reference voltage Jumper pins 1 2 REG on J142 In this configuration an onboard low temperature coefficient 1 25V reference U45 Texas Instruments part number REF3012AIDBZT is c...

Page 41: ...a and clock signals mapped to FPGA pins E21 and F21 respectively The I2C idcode for the PCA9547 device is 0x70 The bus hosts four components SuperClock 2 module 7 series GTX transceiver power supply m...

Page 42: ...42 www xilinx com KC724 GTX Transceiver Characterization Board UG932 v2 2 October 10 2014 Chapter 1 KC724 Board Features and Operation Send Feedback...

Page 43: ...core power to the FPGA For normal operation positions 1 through 6 must be set to the ON position as shown in Figure A 1 Table A 1 Default Jumper Settings Reference Designator Name Board Location Jumpe...

Page 44: ...44 www xilinx com KC724 GTX Transceiver Characterization Board UG932 v2 2 October 10 2014 Appendix A Default Jumper and Switch Positions Send Feedback...

Page 45: ...LVCMOS18 get_ports FMC1_CLK0_M2C_P set_property PACKAGE_PIN AF10 get_ports FMC1_CLK0_M2C_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_CLK0_M2C_N set_property PACKAGE_PIN AD18 get_ports FMC1_CLK1_...

Page 46: ...ts FMC1_LA10_N set_property PACKAGE_PIN AD9 get_ports FMC1_LA11_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA11_P set_property PACKAGE_PIN AE9 get_ports FMC1_LA11_N set_property IOSTANDARD LVCM...

Page 47: ...orts FMC1_LA25_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA25_N set_property PACKAGE_PIN AJ6 get_ports FMC1_LA26_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA26_P set_property PACKAGE_P...

Page 48: ...rts FMC1_HA06_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HA06_P set_property PACKAGE_PIN AJ17 get_ports FMC1_HA06_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HA06_N set_property PACKAGE_P...

Page 49: ...02_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HB02_N set_property PACKAGE_PIN AD2 get_ports FMC1_HB03_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HB03_P set_property PACKAGE_PIN AD1 get_p...

Page 50: ...MOS18 get_ports FMC2_PRSNT_M2C_L set_property PACKAGE_PIN F12 get_ports FMC2_CLK0_M2C_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_CLK0_M2C_P set_property PACKAGE_PIN E13 get_ports FMC2_CLK0_M2C_...

Page 51: ...2_LA10_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA10_P set_property PACKAGE_PIN K30 get_ports FMC2_LA10_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA10_N set_property PACKAGE_PIN K26 g...

Page 52: ...D LVCMOS18 get_ports FMC2_LA24_N set_property PACKAGE_PIN R30 get_ports FMC2_LA25_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA25_P set_property PACKAGE_PIN T30 get_ports FMC2_LA25_N set_proper...

Page 53: ...05_P set_property PACKAGE_PIN AD22 get_ports FMC2_HA05_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_HA05_N set_property PACKAGE_PIN AC24 get_ports FMC2_HA06_P set_property IOSTANDARD LVCMOS18 get...

Page 54: ...t_property PACKAGE_PIN U22 get_ports FMC2_HA20_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_HA20_P set_property PACKAGE_PIN U23 get_ports FMC2_HA20_N set_property IOSTANDARD LVCMOS18 get_ports FM...

Page 55: ...orts FMC2_HB10_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_HB10_N set_property PACKAGE_PIN A11 get_ports FMC2_HB11_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_HB11_P set_property PACKAGE_P...

Page 56: ...orts CM_CTRL_5 set_property IOSTANDARD LVCMOS18 get_ports CM_CTRL_5 set_property PACKAGE_PIN F27 get_ports CM_CTRL_6 set_property IOSTANDARD LVCMOS18 get_ports CM_CTRL_6 set_property PACKAGE_PIN G27 g...

Page 57: ...ANDARD LVCMOS18 get_ports USER_SW2 set_property PACKAGE_PIN C19 get_ports USER_SW3 set_property IOSTANDARD LVCMOS18 get_ports USER_SW3 set_property PACKAGE_PIN A22 get_ports USER_SW4 set_property IOST...

Page 58: ...S18 get_ports DUT_PMB_CLK set_property PACKAGE_PIN H21 get_ports DUT_PMB_DATA set_property IOSTANDARD LVCMOS18 get_ports DUT_PMB_DATA UART GPIO set_property PACKAGE_PIN L17 get_ports USB_GPIO_0 set_pr...

Page 59: ...rts 115_RX1_N set_property PACKAGE_PIN Y2 get_ports 115_TX0_P set_property PACKAGE_PIN Y1 get_ports 115_TX0_N set_property PACKAGE_PIN AA4 get_ports 115_RX0_P set_property PACKAGE_PIN AA3 get_ports 11...

Page 60: ...8_REFCLK0_P set_property PACKAGE_PIN C7 get_ports 118_REFCLK0_N set_property PACKAGE_PIN E8 get_ports 118_REFCLK1_P set_property PACKAGE_PIN E7 get_ports 118_REFCLK1_N set_property PACKAGE_PIN A4 get_...

Page 61: ...N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6...

Page 62: ...62 www xilinx com KC724 GTX Transceiver Characterization Board UG932 v2 2 October 10 2014 Appendix C VITA 57 1 FMC Connector Pinouts Send Feedback...

Page 63: ...erization Kit Answer Record AR 43390 These documents provide supplemental material useful with this guide 1 7 Series FPGAs Overview DS180 2 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual...

Page 64: ...GTX Transceiver Characterization Board UG932 v2 2 October 10 2014 Appendix D Additional Resources These external websites provide supplemental material useful with this guide 15 Texas Instruments Digi...

Page 65: ...ropean Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 Information...

Page 66: ...uipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 EC on the...