HDIO Signals
• Route all HDIO signals as single-ended 50Ω traces.
• The maximum data rate supported on HDIO signals is 250 Mb/s.
• Implement length matching as required by the application PL-based interface mapped to the
HDIO signal groups.
HPIO Signals
HPIO signals can be implemented as high-speed differential signaling such as MIPI interfaces or
other application specific interfaces.
• HPIO P/N pairs should be routed as standard 50Ω single-ended traces.
• The maximum data rate supported on HPIO signals is 2.5 Gb/s.
• Implement length matching as required by the interface used on individual HPIO signal
groups.
• Match P and N signals within an HPIO differential pair to within ±0.5 mils of each other.
• If using MIPI differential signals, length match the MIPI interface HPIO signal groups (pair to
pair) within ±50 mils.
• MIPI differential signals to all other signal spacing should be 2.5 times the distance between
signal to nearest GND plane.
• Match other application-specific HPIO use cases per the HPIO signal group interface
requirement.
PS-GTR Transceivers
PS-GTR transceivers support a maximum transfer rate of 6 Gb/s over each lane.
• To minimize the impedance discontinuity at the SOM connector interface, route the PS-GTR
signals using a 90Ω differential impedance.
• Match P and N differential signals to within ±0.5 mils of each other.
• Route PS-GTR signals in internal routing layers as a stripline structure.
• Route PS-GTR signals with a maximum of two via transitions. Ensure adequate ground return
vias are placed next to the signal vias to minimize crosstalk.
• Route PS-GTR signals to have a maximum via stub length of less than 50 mils. It is a good
design practice to minimize the stub length to avoid reflections.
• PS-GTR differential signals to all other signal spacing should be four times the distance
between the signal to the nearest GND plane.
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021
Carrier Card Design for Kria SOM
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