MIO Bank 501 – PMU MIO Considerations
The Zynq Ult MPSoC platform management unit (PMU) processor has access to a subset of the MIO in bank 501 that are also
available to the clock-capable I/O and should be given special consideration for the implementation of power-down and power control
functionality of the SOM and carrier card design. The SOM power management reserved pins MIO32–34 and are identified in green.
There are also two pins related to optional PMU features made available in the SOM PMU reference implementation that implements
an external shutdown request and can control an external platform watchdog function. These MIO501 optional feature pins are shown
in orange.
• External shutdown request: MIO31 – PMU input pin
• External watchdog toggle: MIO35 – PMU output pin
MIO Bank 501 – UART
RECOMMENDED: The carrier card design should include a UART for board bring-up and initial debug. The Xilinx K26 boot firmware and PetaLinux
BSP default the UART interface to MIO36 and MIO37. It is recommended that carrier card designs use this same mapping to be able to use the Xilinx
provided software references.
Bank 501
MIO #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Peripheral
PMU_GPI
PMU_GPO
PMU_GPO
PMU_GPO
PMU_GPO
UART1
Pin Fct
shtdwn_req
FPD_Pwr_En
PL_Pwr_EN
PS_Pwr_En
WD_out
txd
rxd
MIO Bank 502
MIO bank 502 has no pin reservations relative to the carrier card design, beyond those defined in Zynq Ult Device Technical
Reference Manual (
).
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021
Carrier Card Design for Kria SOM
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