Xilinx MultiLINX Series, Hardware User'S Manual

Page 1: ...Hardware User Guide Alliance 3 1i Printed in U S A Hardware User Guide Cable Hardware MutliLINX Cable FPGA Design Demonstra tion Board CPLD Design Demonstra tion Board Glossary...

Page 2: ...Hardware User Guide...

Page 3: ...g U S Patents 4 642 487 4 695 740 4 706 216 4 713 557 4 746 822 4 750 155 4 758 985 4 820 937 4 821 233 4 835 418 4 855 619 4 855 669 4 902 910 4 940 909 4 967 107 5 012 135 5 023 606 5 028 821 5 047...

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Page 5: ...ct a tool for use specify operations and manage design data These topics are covered in the 2 1i Quick Start Guide Other publications you can consult for related information are the Hardware Debugger...

Page 6: ...tp support xilinx com support techsup tutorials index htm Answers Database Current listing of solution records for the Xilinx software tools Search this database using the search function at http supp...

Page 7: ...ade 100 Courier bold indicates literal commands that you enter in a syntactical statement However braces in Courier bold are not literal and square brackets in Courier bold are literal only in the cas...

Page 8: ...a list of items from which you must choose one or more lowpwr on off A vertical bar separates items in a list of choices lowpwr on off A vertical ellipsis indicates repetitive material that has been...

Page 9: ...Hardware User Guide v Blue underlined text indicates an intrabook link which is a cross reference within a book Click the blue underlined text to open the specified cross reference...

Page 10: ...Hardware User Guide vi Xilinx Development System...

Page 11: ...tions 1 3 XChecker Hardware Drawbacks 1 3 MultiLINX Hardware Advantages 1 3 Previous Cable Versions 1 4 Cable Baud Rates 1 5 MultiLINX Cable and Flying Leads 1 5 External Power for the MultiLINX Cable...

Page 12: ...Downloading Configuration Data 2 13 JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 2 13 Downloading Verification of Configuration Data 2 14 Slave Serial Mode XC3000 2 14 Slave Serial Mode Spartan XC520...

Page 13: ...T Initialize SW2 8 3 15 XChecker Parallel Cable III Connector J2 3 15 Jumper J7 and Tiepoints J10 1 3 3 17 Serial PROM Socket U2 3 17 XC3020A Components 3 18 XC3020A FPGA and Socket U4 3 19 XC3020A Pr...

Page 14: ...on Board Overview 4 1 Software and Download Cable Support 4 1 Printed Circuit Board PCB 4 2 Prototyping Area 4 2 Power Supply 4 2 Demonstration Board Schematics 4 3 Foundation Design Tutorial 4 5 Exam...

Page 15: ...arallel Cable III XChecker Cable Download Cable Schematic Cable Overview There are three cables available for use with Xilinx Alliance and Foundation software The MultiLINX Cable supports USB and RS 2...

Page 16: ...download and readback Note Always set the configuration mode of the device being config ured to slave serial no matter which cable you use Software Support Make sure that you use the appropriate confi...

Page 17: ...ude those devices in the 4000E 4000XL and SPARTAN families whose bitfile size is more than 256K bits The MultiLINX Cable will also support readback for the new Virtex family Note Debug is not availabl...

Page 18: ...ces They also do not have an INIT pin to check for Cyclical Redundancy Check CRC errors during configuration Note To use a parallel download cable prior to the Parallel Cable III to download designs t...

Page 19: ...iLINX Cable is shipped with four sets of flying lead wires A USB Cable and RS 232 Cable with adapter are also supplied For detailed information on the MultiLINX Flying Wires supported modes refer to t...

Page 20: ...DONE DIN PROG INIT RST D0 D1 D3 D4 D5 D6 D7 D2 CS0 CS CS1 CS2 CLK2 OUT WS RS RDWR RDY BUSY CLK2 IN TM STATUS PWR GND CCLK DONE D P DIN PROG INIT RST RT RD TDO TRIG TDI TCK TMS CLK1 IN CLK1 OUT CS0 CS...

Page 21: ...to the VCC red wire and Ground black wire lines of the circuit board that is powering the Xilinx device The external power for the MultiLINX Cable is shown in the following figure R TM USB UNIVERSAL S...

Page 22: ...board power is off Parallel Cable III The Parallel Cable III is a cable assembly which contains a buffer to protect your PC s parallel port and a set of headers to connect to your target system The c...

Page 23: ...flying leads one for FPGAs and one for CPLDs The CPLD leads are labelled JTAG and the FPGA leads are labelled FPGA Each flying lead has a 9 pin 6 signals 3 keys header connector on one end This conne...

Page 24: ...e III and FPGA Flying Leads The following figure shows top and bottom views of the Parallel Cable III including the FPGA and JTAG CPLD headers PROG GND FPGA Flying Lead Connector Connections to Target...

Page 25: ...the CPLD flying leads for configuration make sure to use the JTAG header The following figure shows the connec tions between the Parallel Cable III CPLD flying leads and a target system Parallel Cabl...

Page 26: ...tions VCC Power Supplies VCC 5 V 10 mA typically to the cable To target system VCC GND Ground Supplies ground reference to the cable To target system ground TCK Test Clock Drives the test logic for al...

Page 27: ...of each pin see Table 3 6and Table 3 7 of the FPGA Design Demonstration Board chapter Note If you are using the Xilinx FPGA Design Demonstration Board see the Mode Switch Settings section of the FPGA...

Page 28: ...0 Device Note If you are using the Xilinx FPGA Demonstration Board see the Mode Switch Settings section of the FPGA Design Demonstration Board chapter for specific configuration information Parallel C...

Page 29: ...If you have a different serial port connection you need to provide a DB 9 DB 25 adapter Flying Leads The XChecker Cable is shipped with two sets of flying lead wires The flying lead connectors have a...

Page 30: ...of the XChecker Cable Connection to Host Computer XChecker Cable Flying Lead Connector 1 Header 1 Header 2 Flying Lead Connector 2 DB25 Adapter DB9 Socket Connector 5V Test Fixture Enlarged to show p...

Page 31: ...III is grey The flying lead wires are keyed to fit into the appropriate cable header Use Header 1 for FPGAs and Header 2 for CPLDs XChecker Cable Top View Bottom View Header 2 Header 1 Model DLC4 CAU...

Page 32: ...I TCK TMS and RD TDO pins are connected Note TRST is an optional pin in the JTAG IEEE 1149 1 specification and is not used by XC9500 CPLDs If any of your non Xilinx parts have a TRST pin the pin shoul...

Page 33: ...I Test Data In this signal is used to transmit serial test instructions and data Connect to system TDI pin TCK Test Clock this clock drives the test logic for all devices on boundary scan chain Connec...

Page 34: ...ker Connections to XC4000 Device To configure XC3000 FPGAs the PROG wire is not used This is shown in the following figure In both cases the FPGA must be in the Serial Slave Mode Figure 1 12 XChecker...

Page 35: ...re to the corresponding signal on the target board Next connect VCC to the 5 V on the target board 4 Connect the appropriate pins for device configuration 5 Power up the target system Cable protection...

Page 36: ...te See Table 1 4 If you are using the JTAG Programmer software select the cable manually as follows Output Cable Auto Connect Select your cable type then click OK Download Cable Schematic The followin...

Page 37: ...100 100 100pF 100pF 100pF 100pF 5 1K 1K 01uF 1N5817 X7557 JTAG Header DB25 MALE CONNECTOR FPGA Header 100 300 300 300 300 300 DONE PROG DIN TMS_IN CTRL CLK GND GND D6 BUSY PE SHIELD 15 13 U1 14 7 3 2...

Page 38: ...Hardware User Guide 1 24 Xilinx Development System...

Page 39: ...This chapter contains the following sections Additional MultiLINX Documentation MultiLINX Platform Support MultiLINX Flying Wires Device Configuration Modes Additional MultiLINX Documentation You can...

Page 40: ...98 Win NT 4 0 Solaris 2 6 HP 10 2 MultiLINX Flying Wires The MultiLINX Cable is shipped with four sets of flying lead wires The following figure shows these four sets of MultiLINX flying lead connect...

Page 41: ...Works at multiple voltages 5V 3 3V and 2 5V GND Ground Supplies ground refer ence to cable PWR GND CCLK DONE D P DIN PROG INIT RST RT RD TDO TRIG TDI TCK TMS CLK1 IN CLK1 OUT CS0 CS CS1 CS2 CLK2 IN CL...

Page 42: ...e pin initiates a reconfiguration and indicates that the configura tion process is complete on XC3000 FPGAs DIN Data In Provides configuration data to target system during configuration and is tristat...

Page 43: ...5200 devices RT Read Trigger Pin used to initiate a readback of target FPGA MultiLINX output Hardware Debugger provides Low to High transition on RT to initiate readback RD TDO Read Data MultiLINX inp...

Page 44: ...ystem clock CLK1 OUT Clock Output Drives target system clock Clock can come from either the CLKI IN pin or it can be inter nally generated by the Multi LINX Cable when CLKI IN is unconnected D0 D7 Dat...

Page 45: ...onnect this pin to target system clock to synchronize the read back trigger with target system clock CLK2 OUT Clock Output Drives target system clock Clock can come from either the CLK2 IN pin or it c...

Page 46: ...Wire Set 1 are connected to the VCC red wire and Ground black wire lines of the circuit board that is powering the Xilinx device The minimum input voltage to the cable is 2 5 V 8 A The maximum input...

Page 47: ...n external power supply make sure that the ground of the supply the MultiLINX Cable and the circuit board are all tied together An advantage of the external DC power supply is that no power is taken a...

Page 48: ...llowing table Downloading Configuration Data This section details the connections needed to download configura tion data with the MultiLINX Cable Slave Serial Mode XC3000 The following figure shows in...

Page 49: ...nnec tions for Virtex Spartan XC5200 and XC4000 devices D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT...

Page 50: ...iLINX Cable SelectMAP Mode Virtex The following figure shows in detail the SelectMAP Mode connec tions for Virtex devices D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS...

Page 51: ...The following figure shows in detail the JTAG Mode connections for XC9000 Virtex Spartan XC5200 and XC4000 devices D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TR...

Page 52: ...Serial Mode XC3000 The following figure shows in detail the Slave Serial Mode connec tions for the XC3000 device D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRI...

Page 53: ...2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT DONE D P PROG INIT 4 2 3 1 NOTE Pull up resistors are 4 7k ohm...

Page 54: ...2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT DONE D P PROG INIT 4 2 3 1 NOTE Pull up resistors are 4 7k ohm...

Page 55: ...0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR Vcco RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT DONE D P PROG INIT 4 2 3 1 NOTE Pull up resistors are 4...

Page 56: ...CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR Vcco RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT DONE D P PROG INIT 4 2 3 1 NOTE Pull up resistors are 4 7k ohm Circuit Board XILINX device Mul...

Page 57: ...nnections for verification of configuration data only with Spartan XC5200 and XC4000 devices D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS R...

Page 58: ...in detail the connections for verification of configuration data only with the XC3000 device D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS...

Page 59: ...ode XC3000 The following figure shows in detail the Slave Serial Mode connec tions for synchronous probing using the XC3000 device D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TD...

Page 60: ...Mode connec tions for synchronous probing using Spartan XC5200 and XC4000 devices D0 D1 D2 D3 D4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS RDWR CLK2 I...

Page 61: ...4 D5 D6 D7 RDY BUSY CS2 CS1 CS0 CS WS GND CCLK DIN RT TDI TCK TMS RST TRIG RD TDO PWR VCC RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT DONE D P PROG INIT 4 2 3 1 NOTE Pull up resistors are 4 7k ohm Circu...

Page 62: ...co RS RDWR CLK2 IN CLK2 OUT CLK1 IN CLK1 OUT DONE D P PROG INIT 4 2 3 1 NOTE Pull up resistors are 4 7k ohm Circuit Board XILINX device MultiLINX Connectors VCC VCC Vcco Vcco optional System Clock x U...

Page 63: ...ilies and the Xilinx software development system This chapter contains the following sections Demonstration Board Overview General Components XC4003E Components XC3020A Components Mode Switch Settings...

Page 64: ...ftware Support Two Xilinx software packages can be used with this demonstration board XChecker is a command line text only program available for both PC and Workstation platforms The XChecker Software...

Page 65: ...to provide logic inputs to the FPGAs Program Reset and Spare Active Low push button switches which are common to both FPGAs An XC3000A display for the XC3000 device The display uses eight LED bars in...

Page 66: ...FPGA Demonstration Board Displays General Components This section describes the common components that are found on the FPGA Demonstration Board The following figure shows the compo nent layout of th...

Page 67: ...EMO BOARD XC4003E PC84 XC3020A PC68 RN4 RN3 GND R5 C5 C6 SW3 59 60 R4 R1 R2 44 43 27 28 C8 C7 D17 ASSY 0430822 RESET SW4 SPARE SW5 PROG SW6 Y1 26 C4 11 10 1 2 3 4 5 6 7 8 RN9 C9 LO HI RN13 RN10 RN11 R...

Page 68: ...o connect the unregulated power source The hole with the square pad marked with a is the positive input The other hole marked with a is circuit ground The positive input is connected through the power...

Page 69: ...int triangles the trace cut option for the XC3020A is under its socket and the trace cut option for the XC4003E is under R3 The SPARE signal is pulled High through a 27 kilohm resistor PROG Pushbutton...

Page 70: ...lates it from the switch so it is possible to define the pins as outputs You can also drive the pins from an external source by connecting that signal to the FPGA probe point header The following tabl...

Page 71: ...be on while the FPGA is in its internal clearing state then it should remain off during configuration If the decimal point comes back on a programming error has occurred The decimal points on U6 and U...

Page 72: ...and D9 through D16 connect to the XC4003E You can turn on an LED by driving its corresponding FPGA pin Low with a logic 0 The following table shows the pin connections for the LED indicators Table 3 4...

Page 73: ...on stration Board The oscillator output drives the XC3020A XTL2 input at pin 43 and the XC4003E PGCK1 input at pin 13 Prototype Area The Prototype area is a 0 1 inch grid of holes where you can add ad...

Page 74: ...s solder side are available on the perim eter of this area There are also locations for filter capacitors XC4003E Components This section describes the components on the FPGA Demonstration Board which...

Page 75: ...E 4 CLK 2 OE R 3 U2 1765 7 1 0 RST 1 6 1 5 5 27K 1 2 1 7 1 8 1 4 1 9 1 3 9 11 13 15 17 7 J2A 1 2 J7 CUT OPTION 1 2 560 3 4 7 8 5 6 3 4 5 6 7 8 1 2 560 1 2 560 3 4 7 8 1 2 560 3 4 5 6 5 6 7 8 2 15 MPE...

Page 76: ...rned on and SPE turned off the configuration PROM U2 is reset by the RESET pushbutton SW4 Configuration mode must be set to master serial After a Reset or powerup the first bitstream stored in the ser...

Page 77: ...56 INIT Initialize SW2 8 When this switch is on it connects the XC3020A INIT pin to the XC4003E INIT pin This connection is used to configure FPGAs in a daisy chain with the XC4003E at the head of the...

Page 78: ...onfiguration is complete Connects to XC4003E output pin 53 J2 10 TDI Inputs boundary scan data to the XC4003E Connects to XC4003E pin 15 J2 11a DIN Provides configura tion data during configuration Co...

Page 79: ...gures the XC4003E or the XC4003E and XC3020A connected in a daisy chain The configuration mode must be in the master serial mode to configure from the serial PROM J2 15 INIT Goes Low if CRC error occu...

Page 80: ...XTL1 47 I O 48 I O 49 I O 50 I O 51 I O 53 I O 54 I O 55 I O 56 I O 57 DIN 58 DOUT 59 CCLK 60 U4 XC3020A INP3 5 6 3 4 1 2 1K 7 8 5 6 3 4 1 2 1K 1 2 4 7K 1 4 1 3 1 5 1 6 1 7 1 8 1 9 CUT R2 100K 1 3 R1...

Page 81: ...hrough 84 respectively The XC3020A pins share the XC4003E probe points header XC3020A Configuration Switches SW1 The following sections describe each of the SW1 switches For more information on config...

Page 82: ...ream stored in the serial PROM The number of bitstreams that can be sequentially loaded is limited by the size of the serial PROM SPE Single Program Enable SW1 3 When SPE is on and MPE is off the conf...

Page 83: ...to the data in line of the XC3020A This connection configures FPGAs in a daisy chain with the XC4003E at the head Note MCLK and DOUT should only be used to configure the FPGAs in a daisy chain XCheck...

Page 84: ...J1 7a CCLK Provides clock during configura tion or readback Connects to XC3020A input pin 50 J1 8 N C b J1 9a D P Starts configuration and indicates completion Connects to XC3020A DONE PROGRAM pin 45...

Page 85: ...on Oscillator Components R1 C5 R2 C6 R1 C5 and R2 C6 are two RC networks that connect to the XC3020A at pins 12 and 14 These RC networks are for use in a relaxation oscil lator such as the circuit is...

Page 86: ...1uF the oscillator generates an output frequency of approximately 100 Hz The following figure shows the RC Network waveforms Figure 3 10 RC Network Waveforms The formula for calculating the RC network...

Page 87: ...From the serial PROM single program From the serial PROM multiple program In a daisy chain The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A FP...

Page 88: ...nput The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A FPGA from the serial PROM Table 3 9 Configuring the XC4003E from the XChecker Parallel Ca...

Page 89: ...rom the Serial PROM Single Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE X SW2 2 MPE OFF SW1 3 SPE X SW2 3 SPE ON SW1 4 M0 X SW2 4 M0 OFF SW1 5 M1 X SW2 5 M1 OFF...

Page 90: ...Table 3 13 Configuring the XC4003E from the Serial PROM Multiple Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE X SW2 2 MPE ON SW1 3 SPE X SW2 3 SPE OFF SW1 4 M0...

Page 91: ...8 INIT ON X indicates don t care Table 3 15 Configuring the XC3020A and XC4003E in a Daisy Chain from the Serial PROM Single Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X...

Page 92: ...03E FPGA Note The Parallel Cable III can also be used for FPGA configuration For Parallel Cable III connection information refer to the External Power for the MultiLINX Cable section of the Cable Hard...

Page 93: ...clude the Startup symbol in your design and select the location of the RESET pin Attach pin 56 to an inverter and the GSR pin on the Startup symbol GSR is active High so you must include an inverter b...

Page 94: ...edit the demonstration designs supplied with the Xilinx software tools Note Make backups before making changes to any demonstration design files 1 Place and route the design Produce a routed design de...

Page 95: ...tion switches apply power to the FPGA Demonstration Board This step configures the FPGA when the DONE pin goes High it indicates that the design logic is active 8 Start your configuration software Fo...

Page 96: ...Web site and on the AppLINX CD The Web site location is http support xilinx com support techsup tutorials index htm Please contact your local Sales Repre sentative for a copy of the AppLINX CD Calcula...

Page 97: ...ails the features and support for the CPLD Demonstration Board The demonstration board uses a surface mounted 555 timer with resistor and capacitor values set for 14 Hz operation This oscillator clock...

Page 98: ...area has 299 holes 13 columns x 23 rows for attaching additional circuitry The holes are 0 038 inch diameter on 0 10 inch centers Two pairs of these holes are connected to 5V and GND along the left si...

Page 99: ...to a SERPAC plastic case Model H 65 AC This case can be purchased from SERPAC 619 Commer cial Ave Covina CA 91723 Tel 818 331 0517 Fax 818 331 8584 http www serpac com Demonstration Board Schematics A...

Page 100: ...5 D6 D7 D8 R1 R2 R3 R4 R5 R6 R7 R8 470 470 470 470 470 470 470 470 I O I O I O I O I O GND I O VCC I O I O I O GTS2 VCC GTS1 I O I O I O I O I O I O GCK1 GCK2 GSR I O I O I O I O I O I O VCC GND TDO I...

Page 101: ...ter tutorial which includes the following five design entry methods JCT_SCH schematic only JCT_ABL ABEL only JCT_SABL schematic with ABEL macro JCT_VHD VHDL only JCT_SVHD schematic with VHDL macro Exa...

Page 102: ...with XVHDL macro JCOUNTER VHD TARGET DEVICE XC9536 VQ44 any speed I O Pins CLK input free running clock Q0 Q7 counter outputs OPERATION The counter is triggered on rising edge of the clock CLK The fol...

Page 103: ...ign Flow tutorial in the Foundation Series On Line Help System DEMO BOARD The JEDEC programming file produced by this project can be downloaded into the CPLD Demo Board HW CPLD DEMOBD Example 2 VHDL D...

Page 104: ...innum of Dout signal is p13 14 16 18 19 20 21 22 end jcounter architecture jcounter_arch of jcounter is begin if CLK event and CLK 1 then CLK rising edge Dout 7 downto 1 Dout 6 downto 0 shift Dout 7 d...

Page 105: ...CPLD is an erasable programmable logic device that can be programmed with a schematic or a behavioral design Daisy Chain A daisy chain is a series of bitstream files concatenated in one file It can be...

Page 106: ...onfiguration mode supported by the following MultiLINX devices Virtex Spartan XC9500 XC5200 and XC4000 MultiLINX Cable The MultiLINX cable is a device for configuring and verifying Xilinx FPGAs and CP...

Page 107: ...orted by the MultiLINX device Virtex Slave Serial Mode Slave Serial Mode is a MultiLINX configuration mode supported by the following MultiLINX devices Virtex Spartan XCS5200 and XC3000 Universal Seri...

Page 108: ...Hardware User Guide Glossary 4 Xilinx Development System...