SP601 Hardware User Guide
www.xilinx.com
11
UG518 (v1.1) August 19, 2009
Related Xilinx Documents
Block Diagram
Figure 1-1
shows a high-level block diagram of the SP601 and its peripherals.
Related Xilinx Documents
Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.
See the following locations for additional documentation on Xilinx tools and solutions:
•
ISE:
www.xilinx.com/ise
•
Answer Browser:
www.xilinx.com/support
•
Intellectual Property:
www.xilinx.com/ipcenter
X-Ref Target - Figure 1-1
Figure 1-1:
SP601 Features and Banking
LED
s
DIP
S
witch
GPIO He
a
der
FMC LPC
Exp
a
n
s
ion Connector
10/100/1000
Ethernet GMII
S
partan-6
XC6
S
LX16
U1
P
a
r
a
llel Fl
as
h
U
S
B
JTAG Connector
P
us
h
bu
tton
s
DDR2
Differenti
a
l Clock
Clock
S
ocket
S
MA Clock
IIC EEPROM
a
nd He
a
der
MODE
DIP
S
witch
S
PI x4 or
Extern
a
l Config
U
S
B UART
UG51
8
_01_070
8
09
DED
B
a
nk 0
2.5 V
B
a
nk 3
1.
8
V
B
a
nk 1
2.5V
B
a
nk 2
2.5V