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Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 2:
Power Distribution System
Capacitor Anti-Resonance
One problem associated with combinations of capacitors in a PDS of an FPGA is anti-
resonant spikes in the PDS aggregate impedance. The cause for these spikes is a bad
combination of energy storage elements in the PDS (intrinsic capacitances, discrete
capacitors, parasitic inductances, and power and ground planes).
Anti-resonance can arise between the high-frequency PCB capacitors and the PCB plane
capacitance. The inter-plane capacitance of the power and ground planes generally has
a
high-Q factor. If the high-frequency PCB capacitors also are high-Q, the crossover point
between the high-frequency discrete capacitors and the plane capacitance might exhibit a
high-impedance anti-resonance peak. If the FPGA has a high transient current demand at
this frequency (as a stimulus), a large noise voltage can occur.
To correct this type of problem, the characteristics of the high-frequency discrete capacitors
or the characteristics of the V
CC
and ground planes must be changed, or FPGA activity
shifted to a different frequency away from the resonance.
Capacitor Placement Background
To perform the decoupling function, capacitors should be close to the device being
decoupled.
Increased spacing between the FPGA and decoupling capacitor increases the current flow
distance in the power and ground planes, and it often increases the current path’s
inductance between the device and the capacitor.
The inductance of this current path (the loop followed by current as it travels from the V
CC
side of the capacitor to the V
CC
pin[s] of the FPGA, and from the GND pin[s] of the FPGA
to the GND side of the capacitor[s]), is proportional to the loop area. Inductance is
decreased by decreasing the loop area.
Shortening the distance between the device and the decoupling capacitor reduces the
inductance, resulting in a less impeded transient current flow. Because of typical PCB
dimensions, this lateral plane travel tends to be less important than the phase relationship
between the FPGA noise source and the mounted capacitor.
The phase relationship between the FPGA’s noise source and the mounted capacitor
determines the capacitor’s effectiveness. For a capacitor to be effective in providing
transient current at a certain frequency (for example, the capacitor’s resonant frequency),
the phase relationship must be within a fraction of the corresponding period.
The capacitor’s placement determines the length of the transmission line interconnect (in
this case, the power and ground plane pair) between the capacitor and FPGA. The
propagation delay of this interconnect is the key factor.
FPGA noise falls into certain frequency bands, and different sizes of decoupling capacitors
take care of different frequency bands. Thus, capacitor placement is determined by each
capacitor’s effective frequency.
When the FPGA initiates a current demand change, it causes a small local disturbance in
the PDS voltage (a point in the power and ground planes). To counteract this, the
decoupling capacitor must first sense a voltage difference.
