Xilinx VC707 User Manual Download

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VC707 Evaluation Board

www.xilinx.com

UG885 (v1.2) February 1, 2013

Appendix C

Master UCF Listing

The VC707 board master user constraints file (UCF) template provides for designs
targeting the VC707 board. Net names in the constraints listed in this appendix correlate
with net names on the latest VC707 board schematic. Users must identify the appropriate
pins and replace the net names listed here with net names in the user RTL. See

UG625

Constraints Guide

for more information.

Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connectors J35 and
J37 are connected to 1.8V V

cco

banks. Because each user’s FMC card implements

customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.

Refer to the Virtex-7 FPGA VC707 Evaluation Kit Product Page at

www.xilinx.com/vc707

for the latest FPGA pin constraints file. The constraints file listed in this appendix might
not be the latest version.

VC707 Board UCF Listing

NET GPIO_LED_4_LS   LOC = AR35 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_0_VRN_13
#NET 3N787       LOC = AY34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L1P_T0_13
NET USB_SMSC_NXT LOC = BA35 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L1N_T0_13
NET USB_SMSC_DATA0 LOC = AV36 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L2P_T0_13
NET USB_SMSC_DATA1 LOC = AW36 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L2N_T0_13
NET USB_SMSC_DATA2 LOC = BA34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L3P_T0_DQS_13
NET USB_SMSC_DATA3 LOC = BB34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L3N_T0_DQS_13
NET USB_SMSC_DATA4 LOC = BA36 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L4P_T0_13
NET USB_SMSC_RESET_B LOC = BB36 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L4N_T0_13
NET USB_SMSC_STP LOC = BB32 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L5P_T0_13
NET USB_SMSC_DIR LOC = BB33 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L5N_T0_13
NET USB_SMSC_DATA7 LOC = AW35 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L6P_T0_13
NET USB_SMSC_DATA6 LOC = AY35 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L6N_T0_VREF_13
NET USB_SMSC_DATA5 LOC = AT34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L7P_T1_13
NET SI5324_INT_ALM_LS   LOC = AU34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L7N_T1_13
NET SI5324_RST_LS   LOC = AT36 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L8P_T1_13
NET USB_UART_RX   LOC = AU36 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L8N_T1_13
NET USB_UART_RTS LOC = AT32 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L9P_T1_DQS_13
NET USB_UART_TX   LOC = AU33 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L9N_T1_DQS_13
NET USB_UART_CTS LOC = AR34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L10P_T1_13
NET IIC_SCL_MAIN_LS   LOC = AT35 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L10N_T1_13
NET IIC_SDA_MAIN_LS   LOC = AU32 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L11P_T1_SRCC_13
NET PCIE_WAKE_B_LS LOC = AV33 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L11N_T1_SRCC_13
NET REC_CLOCK_C_P   LOC = AW32 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L12P_T1_MRCC_13
NET REC_CLOCK_C_N   LOC = AW33 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L12N_T1_MRCC_13
NET USB_SMSC_REFCLK_OPTION LOC = AV34 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L13P_T2_MRCC_13
NET PCIE_PERST_LS   LOC = AV35 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L13N_T2_MRCC_13
NET USB_SMSC_CLKOUT   LOC = AY32 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L14P_T2_SRCC_13
NET GPIO_DIP_SW1 LOC = AY33 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L14N_T2_SRCC_13
NET GPIO_DIP_SW2 LOC = BA31 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L15P_T2_DQS_13
NET GPIO_DIP_SW3 LOC = BA32 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L15N_T2_DQS_13
NET GPIO_DIP_SW4 LOC = AW30 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L16P_T2_13
NET GPIO_DIP_SW5 LOC = AY30 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L16N_T2_13
NET GPIO_DIP_SW6 LOC = BA30 | IOSTANDARD=LVCMOS18; # Bank 13 VCCO - VCC1V8_FPGA - IO_L17P_T2_13