90
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
Appendix C:
Master UCF Listing
NET DDR3_D15 LOC = J15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L16N_T2_39
NET DDR3_D8 LOC = K14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L17P_T2_39
NET DDR3_D9 LOC = K13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L17N_T2_39
NET DDR3_D12 LOC = L16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L18P_T2_39
NET DDR3_D13 LOC = L15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L18N_T2_39
NET DDR3_D7 LOC = L12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L19P_T3_39
#NET VTTVREF LOC = L11 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_39
NET DDR3_D3 LOC = M14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L20P_T3_39
NET DDR3_D2 LOC = L14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L20N_T3_39
NET DDR3_DQS0_P LOC = N16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_39
NET DDR3_DQS0_N LOC = M16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_39
NET DDR3_D1 LOC = N13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L22P_T3_39
NET DDR3_DM0 LOC = M13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L22N_T3_39
NET DDR3_D5 LOC = N15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L23P_T3_39
NET DDR3_D0 LOC = N14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L23N_T3_39
NET DDR3_D4 LOC = M12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L24P_T3_39
NET DDR3_D6 LOC = M11 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L24N_T3_39
NET VRP_39 LOC = J11 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_25_VRP_39
#NET 12N119 LOC = AW2 ; # Bank 111 - MGTXTXP3_111
#NET GND LOC = AW6 ; # Bank 111 - MGTXRXP3_111
#NET 12N118 LOC = AW1 ; # Bank 111 - MGTXTXN3_111
#NET GND LOC = AW5 ; # Bank 111 - MGTXRXN3_111
#NET 12N121 LOC = AY4 ; # Bank 111 - MGTXTXP2_111
#NET GND LOC = AY8 ; # Bank 111 - MGTXRXP2_111
#NET 12N120 LOC = AY3 ; # Bank 111 - MGTXTXN2_111
#NET 12N117 LOC = AW10 ; # Bank 111 - MGTREFCLK0P_111
#NET GND LOC = AY7 ; # Bank 111 - MGTXRXN2_111
#NET 12N116 LOC = AW9 ; # Bank 111 - MGTREFCLK0N_111
#NET 12N115 LOC = BA9 ; # Bank 111 - MGTREFCLK1N_111
#NET 12N114 LOC = BA10 ; # Bank 111 - MGTREFCLK1P_111
#NET 12N123 LOC = BA2 ; # Bank 111 - MGTXTXP1_111
#NET GND LOC = BA6 ; # Bank 111 - MGTXRXP1_111
#NET 12N122 LOC = BA1 ; # Bank 111 - MGTXTXN1_111
#NET GND LOC = BA5 ; # Bank 111 - MGTXRXN1_111
#NET 12N125 LOC = BB4 ; # Bank 111 - MGTXTXP0_111
#NET GND LOC = BB8 ; # Bank 111 - MGTXRXP0_111
#NET 12N124 LOC = BB3 ; # Bank 111 - MGTXTXN0_111
#NET GND LOC = BB7 ; # Bank 111 - MGTXRXN0_111
#NET 12N132 LOC = AR2 ; # Bank 112 - MGTXTXP3_112
#NET GND LOC = AP8 ; # Bank 112 - MGTXRXP3_112
#NET 12N133 LOC = AR1 ; # Bank 112 - MGTXTXN3_112
#NET GND LOC = AP7 ; # Bank 112 - MGTXRXN3_112
#NET 12N134 LOC = AT4 ; # Bank 112 - MGTXTXP2_112
#NET GND LOC = AR6 ; # Bank 112 - MGTXRXP2_112
#NET 12N135 LOC = AT3 ; # Bank 112 - MGTXTXN2_112
#NET 12N130 LOC = AT8 ; # Bank 112 - MGTREFCLK0P_112
#NET GND LOC = AR5 ; # Bank 112 - MGTXRXN2_112
#NET 12N131 LOC = AT7 ; # Bank 112 - MGTREFCLK0N_112
#NET 12N5 LOC = W9 ; # Bank 112 - MGTRREF_112
#NET 12N128 LOC = AU9 ; # Bank 112 - MGTREFCLK1N_112
#NET 12N129 LOC = AU10 ; # Bank 112 - MGTREFCLK1P_112
#NET 12N136 LOC = AU2 ; # Bank 112 - MGTXTXP1_112
#NET GND LOC = AU6 ; # Bank 112 - MGTXRXP1_112
#NET 12N137 LOC = AU1 ; # Bank 112 - MGTXTXN1_112
#NET GND LOC = AU5 ; # Bank 112 - MGTXRXN1_112
#NET 12N138 LOC = AV4 ; # Bank 112 - MGTXTXP0_112
#NET GND LOC = AV8 ; # Bank 112 - MGTXRXP0_112
#NET 12N139 LOC = AV3 ; # Bank 112 - MGTXTXN0_112
#NET GND LOC = AV7 ; # Bank 112 - MGTXRXN0_112
#NET 13N97 LOC = AL2 ; # Bank 113 - MGTXTXP3_113
#NET 13N95 LOC = AJ6 ; # Bank 113 - MGTXRXP3_113
#NET 13N96 LOC = AL1 ; # Bank 113 - MGTXTXN3_113
#NET 13N94 LOC = AJ5 ; # Bank 113 - MGTXRXN3_113
NET SFP_TX_P LOC = AM4 ; # Bank 113 - MGTXTXP2_113
NET SFP_RX_P LOC = AL6 ; # Bank 113 - MGTXRXP2_113
NET SFP_TX_N LOC = AM3 ; # Bank 113 - MGTXTXN2_113
NET SGMIICLK_Q0_P LOC = AH8 ; # Bank 113 - MGTREFCLK0P_113
NET SFP_RX_N LOC = AL5 ; # Bank 113 - MGTXRXN2_113
NET SGMIICLK_Q0_N LOC = AH7 ; # Bank 113 - MGTREFCLK0N_113
NET SMA_MGT_REFCLK_N LOC = AK7 ; # Bank 113 - MGTREFCLK1N_113
NET SMA_MGT_REFCLK_P LOC = AK8 ; # Bank 113 - MGTREFCLK1P_113
NET SGMII_TX_P LOC = AN2 ; # Bank 113 - MGTXTXP1_113
NET SGMII_RX_P LOC = AM8 ; # Bank 113 - MGTXRXP1_113
NET SGMII_TX_N LOC = AN1 ; # Bank 113 - MGTXTXN1_113
NET SGMII_RX_N LOC = AM7 ; # Bank 113 - MGTXRXN1_113
NET SMA_MGT_TX_P LOC = AP4 ; # Bank 113 - MGTXTXP0_113
NET SMA_MGT_RX_P LOC = AN6 ; # Bank 113 - MGTXRXP0_113
NET SMA_MGT_TX_N LOC = AP3 ; # Bank 113 - MGTXTXN0_113
NET SMA_MGT_RX_N LOC = AN5 ; # Bank 113 - MGTXRXN0_113
NET PCIE_TX4_P LOC = AG2 ; # Bank 114 - MGTXTXP3_114
NET PCIE_RX4_P LOC = AD4 ; # Bank 114 - MGTXRXP3_114
