72
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
Chapter 1:
VC707 Evaluation Board Features
shows mode switch SW13.
The mode pins settings on SW11 determine if the Linear BPI Flash is used for configuring
the FPGA. DIP switch SW11 also provides the upper two address bits for the Linear BPI
Flash and can be used to select one of multiple stored configuration bitstreams.
shows the connectivity between the onboard nonvolatile Flash devices used for
configuration and the FPGA.
To obtain the fastest configuration speed an external 80 MHz oscillator is wired to the
EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA
over the 16-bit datapath from the Linear BPI Flash memory at a maximum synchronous
read rate of 40 MHz. The bitstream stored in the flash memory must be generated with a
bitgen option to divide the EMCCLK by two.
Table 1-34:
Mode Switch SW11 Settings
Mode Pins
(M2, M1, M0)
Configuration Mode
010
Master BPI
101
JTAG
X-Ref Target - Figure 1-36
Figure 1-36:
Mode Switch
UG885_c1_33_030512
SDA05H1SBD
SW11
R401
220
Ω
0.1 W
1%
R402
220
Ω
0.1 W
1%
VCC2V5
FPGA_M2
FPGA_M1
FPGA_M0
FLASH_A25
FLASH_A24
R396
1.21k
Ω
0.1 W
1%
R397
1.21k
Ω
0.1 W
1%
R398
1.21k
Ω
0.1 W
1%
R399
1.21k
Ω
0.1 W
1%
R400
1.21k
Ω
0.1 W
1%
1
2
3
4
5
10
9
8
7
6
GND
ON
