The core keeps the signal
m_axis_rc_tvalid
asserted over the entire duration of the packet.
The user logic can prolong a beat at any time by pulling down m_axis_rc_tready. The AXI4-
Stream interface signals
m_axis_rc_tkeep
(one per Dword position) indicate the valid Dwords
in the packet including the descriptor and any null bytes inserted between the descriptor and the
payload. That is, the
tkeep
bits are set to 1 contiguously from the first Dword of the descriptor
until the last Dword of the payload. During the transfer of a packet, the
m_axis_rc_tkeep
bits
can be 0 only in the last beat of the packet, when the packet does not fill the entire width of the
interface. The signal
m_axis_rc_tlast
is always asserted in the last beat of the packet.
The
m_axi_rc_tuser
bus provides several optional signals that can be used to simplify the
logic associated with the user side of the interface, or to support additional features. The signal
is_sop[0]
is asserted in the first beat of every packet, when its descriptor is on the bus. When
the straddle option is not in use, none of the other sop and eop indications within
m_axi_rc_tuser
are relevant to the transfer of Completions. The byte enable outputs
byte_en[127:0]
(one per byte lane) indicate the valid bytes in the payload. These signals are
asserted only when a valid payload byte is in the corresponding lane (it is not asserted for
descriptor or null bytes). The asserted byte enable bits are always contiguous from the start of
the payload, except when payload size is 2 Dwords or less. For Completion payloads of two
Dwords or less, the 1s on
byte_en
are not be contiguous. Another special case is that of a zero-
length memory read, when the core transfers a one-Dword payload with the
byte_en
bits all set
to 0. Thus, the user logic can, in all cases, use the
byte_en
signals directly to enable the writing
of the associated bytes into memory.
The following figure illustrates the Dword-aligned transfer of a Completion TLP received from
the link with an associated payload across the requester completion interface. For the purpose of
illustration, the size of the data block being written into user memory is assumed to be n Dwords,
where
n = k*16 + 4
, for some k > 1. The timing diagrams in this section assume that the
Completions are not straddled on the interface. The straddle feature is described in
.
Chapter 4: Designing with the Core
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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