Appendix A
GT Selection and Pin Planning for
CPM4
This appendix provides guidance on gigabit transceiver (GT) selection for applicable Versal
®
devices and some key recommendations that should be considered when selecting the GT
locations. This appendix provides guidance for CPM, PL PCIe
®
and PHY IP based solutions. In
this guide, the CPM related guidance is of primary importance, while the other related guidance
might be relevant and is provided for informational purposes.
A GT Quad is comprised of four GT lanes. GT Quad and ref clock locations for CPM4 are in fixed
locations depending on the desired link configuration (see
). When selecting
GT Quads for the PHY IP based solution with Xilinx PCIe MAC, Xilinx recommends that you use
the GT Quads most adjacent to the Xilinx PCIe macro. While this is not required, it improves
place, route, and timing for the design.
• Link widths of x1, x2, and x4 require one bonded GT Quad and should not split lanes between
two GT Quads.
• A link width of x8 requires two adjacent GT Quads that are bonded and are in the same SLR.
• A link width of x16 requires four adjacent GT Quads that are bonded and are in the same SLR.
• PL PCIe blocks should use GTs adjacent to the PCIe block where possible.
• CPM has a fixed connectivity to GTs based on the CPM configuration.
For GTs on the left side of the device, PCIe lane 0 is placed in the bottom-most GT of the
bottom-most GT Quad. Subsequent lanes use the next available GTs moving vertically up the
device as the lane number increments. This means that the highest PCIe lane number uses the
top-most GT in the top-most GT Quad that is used for PCIe.
For GTs on the right side of the device, PCIe lane 0 is placed in the top-most GT of the top-most
GT Quad. Subsequent lanes use the next available GTs moving vertically down the device as the
lane number increments. This means that the highest PCIe lane number uses the bottom-most
GT in the bottom-most GT Quad that is used for PCIe.
The PCIe reference clock uses GTREFCLK0 in the PCIe lane 0 GT Quad for x1, x2, x4, and x8
configurations. For x16 configurations the PCIe reference clock should use GTREFCLK0 on a GT
Quad associated with lanes 8-11. This allows the clock to be forwarded to all 16 PCIe lanes.
Appendix A: GT Selection and Pin Planning for CPM4
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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