Virtex-6 FPGA Connectivity Kit Getting Started
11
UG664 (v1.4) July 6, 2011
Getting Started with the Connectivity Targeted Reference Design Demo
The Virtex-6 FPGA Connectivity TRD features these components:
•
Virtex-6 FPGA Integrated Block for PCI Express core configured as a
4-lane at 5 Gb/s or 8-lane at 2.5 Gb/s Endpoint for PCI Express, v2.0
•
A performance monitor tracks the PCIe® data bandwidth by measuring data bus
utilization on:
•
AXI4-Stream interface
•
Packet DMA for PCI Express from Northwest Logic, a multichannel DMA that:
•
Supports full-duplex operation with independent transmit and receive paths
•
Provides a packetized interface on the backend similar to LocalLink
•
Monitors data transfers in the receive and transmit directions
•
Provides a control plane interface to access user-defined registers
•
Multiport Virtual FIFO
•
The Memory Interface Controller is delivered through the Virtex-6 FPGA Memory
Interface Generator (MIG) tool.
•
The virtual FIFO is a highly efficient layer around the native interface of the
Virtex-6 FPGA Memory Controller and an external DDR3 memory device.
•
XAUI LogiCORE IP that utilizes serial I/O transceivers to provide a throughput of up
to 10 Gb/s
XAUI TX and XAUI RX blocks align data as per the XGMII format.
•
Control logic to interface between the DMA and the multiport Virtual FIFO.
X-Ref Target - Figure 1
Figure 1:
Block Diagram of the Virtex-6 FPGA Targeted Reference Design
P
a
cket
DMA
S
oftware
Hardware
C2
S
S
2C
C2
S
S
2C
x4 PCIe Link @ 5.0 G
b
/
s
or
x
8
PCIe Link @ 2.5 G
b
/
s
Third P
a
rty IP
FPGA Logic
64-
b
it AXI4-
S
tre
a
m Interf
a
ce @ 250 MHz
Regi
s
ter
Interf
a
ce
Perform
a
nce
Monitor
U
s
er
S
p
a
ce
Regi
s
ter
s
P
a
cket
Control
with CRC
S
2C_Ctrl
S
2C_D
a
t
a
64
GTX T
r
a
n
s
ceiv
er
s
x4 @ 5 G
b
/
s
/ x
8
@ 2.5 G
b
/
s
Integ
r
a
ted Bloc
k
f
or PCI Expre
ss
, v2.0
Wr
a
pper f
or PCI Expre
ss
B
as
e DMA Dr
iv
er
R
a
w D
a
t
a
Dr
iv
er
XA
UI Dr
iv
er
GUI
Xilinx IP
Integr
a
ted Block
s
N
a
tive
Interf
a
ce
of DDR
3
Memory
Controller
M
u
ltiport
Virt
ua
l
FIFO
UG664_01_092
8
10
Control
WR_D
a
t
a
64
C2
S
_Ctrl
C2
S
_D
a
t
a
64
XGMII
TX
XA
UI
GTX T
r
a
n
s
ceiv
er
s
Control
RD_D
a
t
a
64
Control
D
a
t
a
64
XGMII
RX
Control
WR_D
a
t
a
64
Control
D
a
t
a
64
@400 MHz
@200 MHz
@250 MHz
@156.25 MHz
@250 MHz
@250 MHz
@250 MHz
@250 MHz
@156.25 MHz
DDR
3
64
Control
RD_D
a
t
a
64
Control
Control
S
2C_Ctrl
S
2C_D
a
t
a
64
Control
WR_D
a
t
a
64
C2
S
_Ctrl
C2
S
_D
a
t
a
64
R
a
w D
a
t
a
Loop
ba
ck
Control
RD_D
a
t
a
64
Control
WR_D
a
t
a
64
256
256
Control
RD_D
a
t
a
64
P
a
cket
Control
with CRC
Gener
a
tor
Checker
Summary of Contents for Virtex-6 FPGA
Page 1: ...Virtex 6 FPGA Connectivity Kit Getting Started Guide UG664 v1 4 July 6 2011 XPN 0402826 03...
Page 4: ...Virtex 6 FPGA Connectivity Kit Getting Started www xilinx com UG664 v1 4 July 6 2011...
Page 6: ...6 www xilinx com Virtex 6 FPGA Connectivity Kit Getting Started UG664 v1 4 July 6 2011...
