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Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Virtex-6 FPGA IBERT Reference Design
Getting Started with the Virtex-6 FPGA IBERT Reference Design
This Virtex-6 FPGA Connectivity Kit comes with an Integrated Bit Error Ratio Test (IBERT)
reference design available on the CompactFlash. The demonstration shows the capabilities
of the Virtex-6 LXT device using the GTX transceivers running at 3.125 Gb/s line rates. The
GTX transceivers can successfully operate at line rates from 750 Mb/s to 6.6 Gb/s.
The Virtex-6 FPGA IBERT reference design has these components:
•
Virtex-6 FPGA GTX transceivers running at 3.125 Gb/s
•
The IBERT v2.0 reference design available through the CORE Generator tool for
IP delivery
The design also includes a pseudo-random bit sequence (PRBS) pattern generator and
checker.
•
Four GTX transceivers in the Virtex-6 LX240T FPGA are accessed through these
channels in the IBERT reference design:
•
SMA (two channels)
•
SATA (two channels)
Note:
The demonstration is for SMA and SATA external loopback scenarios only.
IBERT Hardware Demonstration Setup Instructions
This section describes how to set up the hardware for the IBERT reference design
demonstration. The IBERT reference design is provided as an FPGA programming file on
the CompactFlash.
1.
This equipment is needed to run the demonstration:
•
Virtex-6 FPGA Connectivity Kit
•
PC system with USB port
•
Monitor, keyboard, and mouse
•
ISE Design Suite installed on the PC system
Summary of Contents for Virtex-6 FPGA
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