36
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Installation and Licensing of ISE Design Suite
4.
View the PCIe statistics in Performance Monitor (see
). Click
PCIe Statistics
to view data transfer numbers on the PCIe interface.
Congratulations! The system performance of the Virtex-6 FPGA Connectivity Kit has been
evaluated using the pre-built demonstration design. This design includes the built-in
integrated block for PCI Express (4-lane, 5 GT/s configuration for PCI Express v2.0), XAUI
LogiCORE IP, a Virtual FIFO memory controller designed to interface to the onboard
DDR3 SODIMM device, and a third-party DMA controller for PCI Express.
Installation and Licensing of ISE Design Suite
This Virtex-6 FPGA Connectivity Kit comes with an entitlement to a full seat of the ISE
Design Suite: Embedded Edition that is device locked to a Virtex-6 LX240T FPGA. This
software can be installed from the DVD or the Web installer can be downloaded from
http://www.xilinx.com/support/download/index.htm
For detailed information on licensing and installation, refer to UG631,
ISE Design Suite:
Installation, Licensing, and Release Notes
, located on the Xilinx documentation site at
http://www.xilinx.com/support/documentation
Downloading and Installing Tool Licenses
1.
Visit the Xilinx software registration and entitlement site at
http://www.xilinx.com/getproduct
to access the Xilinx product download and
licensing site (
X-Ref Target - Figure 27
Figure 27:
PCIe Statistics in the Performance Monitor
UG664_15_091010
Summary of Contents for Virtex-6 FPGA
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