60
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Next Steps
Multiport Virtual FIFO and Memory Controller Block
shows the design module for the multiport virtual FIFO and memory controller
shows the design file structure.
X-Ref Target - Figure 56
Figure 56:
Multiport Virtual FIFO and Memory Controller Block Design Module
X-Ref Target - Figure 57
Figure 57:
Multiport Virtual FIFO and Memory Controller Design FIles
UG664_20_060110
N
a
tive
Interf
a
ce
of DDR
3
Memory
Controller
M
u
ltiport
Virt
ua
l
FIFO
Control
WR_D
a
t
a
Control
RD_D
a
t
a
64
64
Control
WR_D
a
t
a
64
@400 MHz
@200 MHz
@250 MHz
@156.25 MHz
@250 MHz
@250 MHz
DDR
3
64
256
256
Control
RD_D
a
t
a
64
Control
WR_D
a
t
a
Control
RD_D
a
t
a
64
64
Control
WR_D
a
t
a
64
Control
RD_D
a
t
a
64
UG664_21_090
8
10
v6_pcie_10Gdm
a
_ddr
3
_x
au
i_
a
xi
de
s
ign
s
o
u
rce
virt
ua
l_fifo
ip_core
s
mig
Summary of Contents for Virtex-6 FPGA
Page 1: ...Virtex 6 FPGA Connectivity Kit Getting Started Guide UG664 v1 4 July 6 2011 XPN 0402826 03...
Page 4: ...Virtex 6 FPGA Connectivity Kit Getting Started www xilinx com UG664 v1 4 July 6 2011...
Page 6: ...6 www xilinx com Virtex 6 FPGA Connectivity Kit Getting Started UG664 v1 4 July 6 2011...
