Virtex-6 FPGA Connectivity Kit Getting Started
63
UG664 (v1.4) July 6, 2011
Next Steps
Simulating the Connectivity TRD
A complete simulation environment is provided with the Virtex-6 FPGA Connectivity
TRD. For more details on the simulation environment and the associated simulation files,
refer to the “Simulation” section in the “Getting Started” chapter in
Virtex-6 FPGA
Connectivity Targeted Reference Design with AXI4 Protocol User Guide
.
Reusing the DMA IP from Northwest Logic
The Packet DMA Controller included in the Virtex-6 FPGA Connectivity Kit is an
evaluation version of the Northwest Logic PCIe Packet DMA IP Core. This 64-bit DMA IP
core is optimized for the Virtex-6 FPGA architecture. The DMA design deliverables are:
•
Simulation model
•
Hardware evaluation netlist (time-limited to 12 hours)
Orders for the full production version of the Northwest Logic PCIe Packet DMA IP core
can be placed at
http://www.nwlogic.com/packetdma
.
Modifications to the Connectivity TRD
The Virtex-6 FPGA Connectivity TRD is a framework for system designers to derive
extensions or modify their designs. Additional possible design enhancements,
modifications, and reconstructions with custom IPs and design blocks are described in the
“Designing with the TRD Platform” chapter in
,
Virtex-6 FPGA Connectivity Targeted
Reference Design with AXI4 Protocol User Guide
.
Summary of Contents for Virtex-6 FPGA
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