ZC706 Evaluation Board User Guide
92
UG954 (v1.5) September 10, 2015
Appendix C
Master Constraints File Listing
The master Xilinx Design Constraints (XDC) file template for the ZC706 board provides for
designs targeting the ZC706 evaluation board. Net names in the constraints listed below
correlate with net names on the latest ZC706 evaluation board schematic. Users must
identify the appropriate pins and replace the net names with net names in the user RTL. See
Vivado Design Suite User Guide: Using Constraints
(
) for more information.
For detailed I/O standards information required for a particular interface, users can refer to
the constraint files generated by tools like the Memory Interface Generator (MIG) and Base
System Builder (BSB).
The FMC connectors J37 and J5 are connected to 2.5V V
ADJ
banks. Because different FMC
cards implement different circuitry, the FMC bank I/O standards must be uniquely defined
by each customer.
Note:
The constraints file listed in this appendix might not be the latest version. Always refer to the
Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit product page (
for the latest pins constraints file.
ZC706 Evaluation Board XDC Listing
#Clocks
set_property PACKAGE_PIN G9 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
set_property PACKAGE_PIN H9 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN AG14 [get_ports USRCLK_N]
set_property IOSTANDARD LVDS_25 [get_ports USRCLK_N]
set_property PACKAGE_PIN AF14 [get_ports USRCLK_P]
set_property IOSTANDARD LVDS_25 [get_ports USRCLK_P]
set_property PACKAGE_PIN AD19 [get_ports USER_SMA_CLOCK_N]
set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N]
set_property PACKAGE_PIN AD18 [get_ports USER_SMA_CLOCK_P]
set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P]
set_property PACKAGE_PIN W7 [get_ports SMA_MGT_REFCLK_N]
set_property PACKAGE_PIN W8 [get_ports SMA_MGT_REFCLK_P]
set_property PACKAGE_PIN AC7 [get_ports SI5324_OUT_C_N
set_property PACKAGE_PIN AC8 [get_ports SI5324_OUT_C_P
set_property PACKAGE_PIN AE20 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
