IC404:
R5F364AENFA (DIGITAL P.C.B.)
Microprocessor
*
No replacement part available. /
サービス部品供給なし
■
IC DATA
Timer (16-bit)
Internal peripheral functions
Inputs (timer B): 6
Three-phase motor control circuit
Outputs (timer A): 5
Watchdog timer
(15-bit)
Remote control signal
receiver
(2 circuits)
PWM function (8-bit x 2)
CEC function
Real-time clock
VCC1 ports
VCC2 ports
A/D converter
(10-bit resolution X 26 channels)
System clock generator
PLL frequency synthesizer
On-chip oscillator (125 kHz)
X
IN
-X
OUT
X
CIN
-X
COUT
Port P0
8
Port P1
8
Port P1
8
Port P3
8
Port P4
8
Port P5
8
Port P10
8
Port P9
8
Port P8
8
Port P7
8
Port P6
8
ISP
USP
INTB
SB
CRC arithmetic circuit
(CRC-CCITT or CRC-16)
DMAC (4 channels)
Voltage detecter
On-chip debugger
Power-on reset
Multiplier
Memory
ROM
RAM
FB
A1
FLG
PC
UART or
clock synchronous serial I/O
Clock synchronous serial I/O
Multi-master I
2
C-bus interface
(6 channels)
(8 bit x 2 channels)
(1 channel)
D/A converter
(8-bit resolution X 2 circuits)
M16C/60 series
Microprocessor core
R0L
R0H
R1H
R1L
R2
R3
FB
A1
A0
MICROPROCESSOR
IC404
R5F364AENFA
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CLAMP_SW
FPGA_PROG
FPGA_DONE
FPGA_INITN
UNCLAMP_SW/N_CE
CLAMP_MTR1
CLAMP_MTR2
TRAY_MTR1
TRAY_MTR2
STBY_CNT/N_EMP
TRAY_SW
TRCLOSE_SW
TROPEN_SW
DAC_N_RST
DAC_SCL
DAC_SDA
WR_BUSY
WR_CK
WR_MISO
WR_MOSI
PRVR
PRVL
PRVD
KEY2
KEY1
KEY0
LOAD-
LOAD+
FPGA_DSDMUTE
FPGA_DOP_DSDPCM
FPGA_DOP_DSDRATE
EX_N_CS
EX_N_IC
FL_PON
FL_N_RST
AVSS
FL_N_CS
VREF
AVCC
NC
FL_EX_MOSI
FL_EX_CLK
PULSE_DET
MTR_CTL_DA
DIR_MOSI
DIR_MISO
DRI_SCK
BYTE
CNVSS
DIR_N_RST
DIR_N_CS
N_RST
XOUT
VSS
XIN
VCC1
N_NMI
REM_REAR
SSP2_N_YISO_IRQ
REM
RY_AUDIO
SSP2_YISO
SSP2_N_YOSI_IRQ
SSP2_YOSI
A_MUTE
SEL_DIR_BYPASS
I2SSEL_DSDPCM
DAC_A_MUTE
SYS_RXD
SYS_TXD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
FPGA_IO0
FPGA_IO1
CD_YIVO
CD_YOVI
CD_PWR
CD_SPDIF_RQ
CD_MUTE
DIR_N_INT
FPGA_IO2
PI_DVDRST
FPGA_JTAGEN
SW_CD_OTHER
CD_PWR_DET
ACPWR_DET
PWR_RY
DPWR_ON
VSS
FPGA_RRESET
VCC2
LED_PWR
SSP2_PON
SSP2_N_IC
SSP2_USB_RDY
SSP2_YISO_MUTE
SSP2_DSD_PCM
SSP2_N_DSPSTOP
SSP2_YOSI_MUTE
FPGA_SELA
FPGA_SELB
FPGA_SELC
43
CD-S3000
CD-S30
0
0
Summary of Contents for CD-S3000
Page 6: ... FRONT PANELS U K A B G L V J models T model 6 CD S3000 CD S3000 ...
Page 7: ... REAR PANELS U V models U model V model Bottom view 7 CD S3000 CD S3000 ...
Page 8: ...A B G L models K model T model A model B G models 8 CD S3000 CD S3000 ...
Page 9: ...J model 9 CD S3000 CD S3000 ...
Page 86: ...86 CD S3000 CD S3000 ...
Page 87: ...MEMO 87 CD S3000 CD S3000 87 ...
Page 88: ...CD S3000 ...