Yamaha CDX-E200, Service Manual

CDX-E200

CDX-E200

Pin No.

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

Function

Loop filter terminal for DSL

Loop filter terminal for PLL

Loop filter terminal for VCO

(+5)

Power supply for analog circuit (for AD of DSL, PLL, DA output blocks)

(+5)

GND for analog circuit (for AD of DSL, PLL, DA output blocks)

(GND)

EFM signal output

(NC)

With command defaulted : PLL extract clock output PCK when IOSEL=H, frame re-synchronous signal RESY when IOSEL=L

These settings can be reversed by command (RESY when IOSEL=H).

(NC)

Flag signal output

(NC)

Sub-code CRC check result output  (H : OK, L : NG)

(NC)

L : Normal mode

(GND)

H : • For internal master clock, VCO2 output clock for jitter adsorbing PLL is used instead of Xtal

oscillation output (X2).

• VCO2 is always fixed to oscillation mode regardless of VCO2 oscillation stop command or

resetting (/RST=L) and Xtal oscillation is stopped.

GND for oscillation circuit

Crystal oscillation circuit input terminal

Crystal oscillation circuit output terminal

Power supply for oscillation circuit

(+5)

PLL loop filter terminal for jitter adsorption

(GND)

GND for audio DAC

PEM output terminal 1C

PEM output terminal 1D

PEM output terminal 2D

PEM output terminal 2C

Power supply terminal for audio DAC

Deemphasis detect signal output

(NC)

384fs clock output (At the CK384 pin, output does not stop while /RST=L.)

(NC)

Xtal system when command is defaulted. Signal processing system when command is switched

Mode selecting terminal

(+5)

Test mode setting terminal (Normal : H)

(+5)

Sub-code data read clock input

Sub-code serial output (SBCK effective) when command is defaulted.

PACK data usable (SBCK2 effective) when command is switched

Clock input for sub-code serial output (with pull-up resistor)

(NC)

Sub-code frame clock signal output when command is defaulted (fCLDCK=7.35kHz)

PACK synchronous signal when command is switched

Interpolation flag signal output  (H : INTERPOLATION)

(NC)

When IOSEL=H, L : NORMAL H : TEST2

(GND)

Emphasis control in accordance with DEMP0

When IOSEL=L, external DEMP1 input terminal

For emphasis control, DEMP0, OR of DEMP1, DEMP1, forced OFF or forced ON is selected by command.

When command is defaulted, DEMP0 and OR of DEMP1

SRDATA input (effective only when IOSEL=L)

(NC)

LRCK input (effective only when IOSEL=L) H : Lch data, L : Rch data

(NC)

BCK input (effective only when IOSEL=L)

(NC)

I/O

I/O

I/O

I/O

I

I

O

O

O

O

I

I

I

O

I

O

O

O

O

O

O

I

O

O

I

I

I

O

I

O

O

I

I

I

I

Name

DSLF

PLLF

VCOF

AVDD2

AVSS2

EFM

PCK/

RESY

FLAG

CRC

XSEL

VSS

X1

X2

VDD

VCOF2

AVSS1

OUT1C

OUT1D

OUT2D

OUT2C

AVDD1

DEMPO

CK384

IOSEL

TEST

SBCK2

SUBC

SBCK

CLDCK

IPFLAG

DEMPI

/TEST2

SDATI

LRCKI

BCKI

IC102 : MN35511AL
Signal Processor & Controller

16