CVP-205/CVP-205M
28
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VA5
VA4
VA3
VA2
VA1
VA0
/VWR
/VCE
/VRD
/RES
NC
NC
/RD
/WR
SEL2
SEL1
OSC1
OSC2
/CS
A0
Vdd
D0
D1
D2
D3
D4
D5
D6
D7
XD3
O
O
O
O
O
O
O
O
-
I
-
-
I
I
I
I
I
O
I
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
VRAM address bus
VRAM read/write
Memory control
Not used
Initial clear
Not used
Not used
Read strobe
Write strobe
Bus select
Bus select
Clock
Clock
Chip select
Data mode select
Power supply
Data bus
Data bus output for 4 bit dot
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
XD2
XD1
XD0
XECL
XSCL
Vss
LP
WF
YDIS
YD
YSCL
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
VA7
VA6
NC
O
O
O
O
O
-
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
-
Data bus output for 4 bit dot
S driver enable, chain clock
Data bus shift clock
Ground
X driver latch pulse
Frame signal for X/Y driver
Power down signal for displaying off mode
Scan start signal
Scan shift clock
VRAM data bus
VRAM address bus
Not used
SED1335F0B (XQ595A00) LCDC (LCD Controller)
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
MCLK
CLATCH
CCLK
CDATA
384//256
X2MCLK
ZEROR
DEEMP
96//48
AGND
OUTR+
OUTR-
FILTR
I
I
I
I
I
I
I
O
I
I
I
O
O
O
Digital Ground
Master Clock Input. Connect to an external
clock source at either 256, 384 or 512 Fs.
Latch input for control data. This input is
rising-edge sensitive.
Control clock input for control data. Control
input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.
Serial control input, MSB first, containing 16 bits
of unsigned data per channel. Used for specifying
channel-specific attenuation and mute.
Selects the master clock mode as either 384
times the intended sample frequency (HI) or
256 times the intended sample frequency (LO).
The state of this input should be hardwired to
logic HI or logic LO, or may be changed while
the AD1854 is in power-down/reset. It must not
be changed while the AD1854 is operational.
Selects internal clock doubler (LO) or
internal clock = MCLK (HI).
Right Channel Zero Flag Output. This pin
goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
D e - E m p h a s i s . D i g i t a l d e - e m p h a s i s i s
enabled when this input signal is HI. This is
used to impose a 50 µs/15 µs response
characteristic on the output audio spectrum
at an assumed 44.1 kHz sample rate.
Selects 48 kHz (LO) or 96 kHz Sample
Frequency Control.
Analog Ground
Right Channel Positive line level analog output.
Right Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection.
Bypass and decouple the voltage reference
with parallel 10 µF and 0.1 µF capacitors to the
AGND.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGND
OUTL-
OUTL+
AVDD
FILTB
IDPM1
IDPM0
ZEROL
MUTE
/PD//RST
L//RCLK
BCLK
SDATA
DVDD
I
O
O
I
O
I
I
O
I
I
I
I
I
I
Analog Ground
Left Channel Negative line level analog
output.
Left Channel Positive line level analog
output.
Analog Power Supply. Connect to analog 5
V supply.
Filter Capacitor connection, connect 10 µF
capacitor to AGND.
Input serial data port mode control one.
With IDPM0, defines one of four serial
modes.
Input serial data port mode control zero.
With IDPM1, defines one of four serial
modes.
Left Channel Zero Flag Output. This pin
goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog
outputs. Deassert LO for normal operation.
/Power-Down//Reset. The AD1854 is
placed in a low power consumption mode
when this pin is held LO. The AD1854 is
reset on the rising edge of this signal. The
serial control port registers are reset to the
default values. Connect HI for normal
operation.
Left//Right clock input for input data. Must
run continuously.
Bit clock input for input data. Need not run
continuously; may be gated or used in a
burst fashion.
Serial input, MSB first, containing two
channels of 16, 18, 20, and 24 bits of twos
complement data per channel.
Digital Power Supply Connect to digital 5 V
supply.
AD1854JRSRL (XY782A00) DAC (Digital to Analog Converter)
Summary of Contents for Clavinova CVP-103M
Page 34: ...CVP 205 CVP 205M 34 DM Circuit Board 2NA V716590 2 2 Pattern side ...
Page 37: ...B B PNR Circuit Board CVP 205 CVP 205M 37 2NA V713520 2 1 ...
Page 38: ...ENC Circuit Board B B CVP 205 CVP 205M 38 Pattern side Pattern side 1 PNR ENC 2NA V713520 2 ...
Page 43: ...to DM CN10 SWX Circuit Board CVP 205 CVP 205M 43 2NA V716050 1 Pattern side Component side ...
Page 100: ...CVP 205 CVP 205M 24 SIDE BOARD ASSEMBLY Top view Side view 1 9 8 6 6a 6b 11 7 7 4 2 3 5 ...
