Yamaha DRX-2 Service Manual Download

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DRX-2

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are available at pin 17/16 and pin 12/13 of [7004] as
symmetrical signals.

Afterwards an Op-Amp. [7003] (line driver & converting to
unsymmetrical signal, gain = 1), which is also working as
low-pass-filter to increase signal performance (noise,
distortions,...), is passed. Then both signals (“ALDAC” &
“ARDAC”) are directly routed to the rear cinch output and
also used in the audio-I/O for further processing. The DAC
has also a mute possibility, which can be activated by
setting pin 23 to 5V via [7001]. This mute is controlled
either by the dig. board (“D_IKLL”-line) or the “IPFAIL”-
signal from power-supply-unit (in this case it’s the
combination of “A_KILL” and “IPFAIL”).

If the DAC is muted externally via pin 23 or if there are no
audio data available (e.g. “D_DATA0”-line zero), the
output pins 8 and 22 of the DAC change to high (+ 5V).
These two signals are then combined with diode pos.
6006. After decoupling via [7009] the signal “DAC_MUTE”
is used as mute signal for the mute transistors [7415],
[7416] for cinch rear out.

b) PCBs with UDA1334BTS [7001]:
The conversion of analog audio signals from the record-
selector [7501] in the I/O (“ALADC”- & “ARADC”) is done
via UDA1361TS [7005]. This IC can process input signals
up to 2Vrms by using external resistors [3039], [3041] in
series to the input pins. As the level from the DVIO-Board
is only 1Vrms a 6dB step can be performed by setting pin 7
of [7005] to 3,3V via [7006] and the “PWONSW”-line
controlled by the CC-P to use the whole dynamic range of
the ADC. All required clock signals are generated on the
dig. board and only the audio data (“A_DAT”-line) are
routed from Ana- to Dig.-PCB for further processing.

The transformation of dig. audio back into the analog
domain is done by UDA1334BTS [7001]. All necessary
clock signals are coming from the dig. board and dig.
audio data (“D_DATA0”-line) are converted into analog
signals, which are available at pin 14 and pin 16 of [7001].
Afterwards an Op-Amp. [7002] (line driver & level
adaptation, gain = 2) which is also working as low-pass-
filter to increase signal performance (noise, distortions,...),
is passed. Then both signals (“ALDAC” & “ARDAC”) are
directly routed to the rear cinch output and also used in the
audio-I/O for further processing. The DAC has also a mute
possibility, which can be activated by setting pin 8 to 3,3V
via [7003]. This mute is controlled either by the dig. board
(“D_IKLL”-line) or the “IPFAIL”-signal from power-supply-
unit (in this case it’s the combination of “A_KILL” and
“IPFAIL”).

In addition to that the DAC [7001] and the cinch outputs
can be killed (muted) in case of “digital silence” by the
circuit around [7008], [7009] and [7010], when no audio
data are available (e.g. “D_DATA0”-line zero).

This function can be also activated via the “ION”-line (set
to high during any stand-by mode). To avoid signal
distortions (clipping) the mute transistors for cinch rear out
[7415], [7416] are decoupled via [7011].