DRX-2
169
■
SCHEMATIC DIAGRAM
DIGITAL (Digital Board Chrysalis 2.1): 1394
DVDD
AVDD
NC
PLLGND
DGND
AGND
DECODER/
BIAS
DATA
INTERFACE
LINK
RECEIVED
CONTROL
STATE
MACHINE
LOGIC
TRANSMIT
CLOCK
PLL
XTAL OSC.
ENCODER
DATA
GENERATOR
CURRENT
AND
VOLTAGE
TEST1
TEST0
C|LKON
ISO_
LPS
CPS
PLLVDD
R0
R1
TPBIAS0
TPA0+
TESTM
TPA0-
TPB0+
TPB0-
XI
XO
TIMER
ARBITRíN
AND
PD
RESET_
CNA
PC2
PC1
PC0
D7
D6
D5
D4
D3
D2
D1
D0
CTL1
CTL0
LREQ
SYSCLK
TESTPIN
GND
VDD
RESERVED
LINK
I205 H11
I206 G4
I207 A3
I208 B3
I209 B3
I210 C2
I211 B7
I212 C7
I213 D6
I214 D6
I215 A6
I216 B6
1%
I217 A8
I218 C7
I219 C7
I220 G12
I221 G12
I222 C7
I223 G12
I224 G8
I225 C7
I226 C7
I227 C7
F209 C13
F210 C13
F211 C13
F212 C13
F213 C13
F214 C13
F215 C13
F216 D13
F217 C13
I200 H4
I201 F2
I202 G2
not used
not used
I203 H2
I204 I2
4204 G12
4205 A4
5200 F2
5201 F5
5202 G2
5203 H2
5204 I1
6200 G4
7200 A5
7201 B12
7202 H5
F1201 B1
F1202 A1
F1203 A1
F1204 A2
F1205 A2
F200 D12
F201 C9
F203 C3
F204 C13
F205 C13
F206 C13
F207 C13
F208 C13
3291 I13
3292 I13
3293 I13
3294 F12
3295 F12
3296 F12
3297 F8
3298 F8
3299 F8
3315 F8
3316 F8
3317 F8
not used
3318 F8
3319 F8
3320 F13
4201 D6
4202 D6
4203 G12
3271 G12
3272 G12
3273 G8
3274 F12
3275 G5
3276 G7
3277 F12
3278 F12
3279 F12
3280 A7
3281 A7
3282 A8
allways present
PHY
1%
3283 A2
3284 A8
3285 A6
3286 H13
3287 H13
3288 H13
3289 H13
3290 I13
3251 E12
3252 E12
3253 D2
3254 E12
3255 E13
3256 E13
3257 E13
3258 E13
3259 E13
3260 F12
3261 E3
3262 F8
not used
3263 F8
3264 F8
3265 G8
3266 G8
3267 G8
3268 G8
3269 G8
3270 G12
3232 C2
3233 C2
3234 C6
3235 C13
3236 C7
3237 D12
3238 C6
3239 D12
3240 C2
3241 D12
3242 C7
3243 D12
1%
not used
not used
not used
3244 D12
3245 D6
3246 E12
3247 E12
3248 D7
3249 E12
3250 E12
3215 C12
3216 B6
3217 C12
3218 C12
3219 D13
3220 B7
3221 C12
3222 C12
3223 B6
3224 C12
3225 C7
3226 C12
1%
3227 C12
3228 C6
3229 C12
3230 D13
3231 C7
2222 I3
2223 I3
2224 I4
2225 I4
2226 I4
2227 I4
2228 I5
2229 I5
2230 I5
2231 I6
2232 I6
2233 I6
2234 I6
3200 E6
3202 F12
3203 H5
3204 D6
3205 A2
3206 B7
3207 B8
3208 B7
3209 B8
3210 C12
3211 C12
3212 B2
3213 B3
3214 C12
B
C
D
E
F
G
H
I
A
B
C
D
not used
1%
2214 H2
2215 H2
2217 I2
2218 I2
2219 I2
2220 I2
2221 I3
6
7
8
9
10
11
12
13
14
1
2
3
DV_IN Only
not used
1%
4
5
6
7
8
9
10
11
12
13
14
A
1203 A1
2200 B2
2201 C2
2202 D1
2203 D2
2204 D2
2205 D2
2206 G3
2207 F2
2209 G2
2210 G2
2212 H1
1
2
3
4
5
allways present
BOARD_ID
not used
E
F
G
H
I
1200 C1
1201 D1
33R
3222
33R
3226
I220
3272
100R
4K7
3250
56R
3232
3270
100R
3254
33R
3320
10K
3274
100R
3277
100R
4204
3297
100R
F206
3259
4K7
I215
3268
4K7
10R
3231
100u
2212
10K
3282
PDTC144EU
7202
56R
3213
3215
33R
4K7
3286
I221
100n
2218
3209
100n
2231
1R0
3238
10R
F200
I204
33R
3243
1R0
3261
3245
10R
F203
100R
3318
3221
33R
100R
3319
6200
TLMH3100
F217
100R
3279
10K
3283
2233
100n
I224
5202
100R
3315
4K7
3292
3239
33R
F210
2204
100n
F211
F208
3205
6K34
F209
100n
2209
I226
2232
100n
3290
4K7
3227
33R
F207
I216
100R
3260
I201
2229
100n
10R
3242
3236
4K7
3267
10R
33R
3237
33R
3211
3288
4K7
3253
1R0
33R
3251
82R
3224
2227
100n
I211
2205
100n
3298
100R
100n
2234
100n
2221
I214
100R
3278
10K
3235
10K
3219
2217
100n
2203
F1203
12p
5K1
3240
10K
3285
33R
3217
2
3
4
5
6
7
8
2207
100n
CSS5004
1200
1
100n
2225
2223
100n
2214
100n
4202
I210
I209
10R
3220
33R
3246
4K7
3287
F214
4K7
3269
3258
22K
33R
3273
2200
1u0
10K
3203
36
35
34
38
59
60
3218
33R
57
58
56
40
41
53
2
29
28
27
37
16
43
44
45
46
47
20
21
22
14
63
64
25
26
61
62
23
15
1
54
55
19
6
7
8
9
10
11
12
13
17
18
50
30
31
42
51
52
3
24
4
5
7200
PDI1394P25
PDI1394P25
32
33
39
48
49
F216
33R
3247
I217
4203
3293
4K7
F1204
3255
4K7
3280
10K
3284
1R0
33R
3244
33R
3249
100n
2228
I219
I218
10R
3228
F205
I223
10K
3207
3262
4K7
F204
I205
10R
3234
330R
3275
5201
24
35
44
54
61
70
3200
10K
78
84
90
95
107
113
120
132
138
12
18
8
71
9
104
RESET_
42
SCLK
88
1
62
2
63
3
64
6
16
144
17
130
2
50
3
51
4
52
5
58
6
59
7
72
PHYD7
73
1
49
10
65
11
66
12
67
13
68
14
105
15
129
PHYCTL1
85
PHYD0
82
PHYD1
81
PHYD2
80
PHYD3
79
PHYD4
76
PHYD5
75
PHYD6
74
HIFWAIT
41
37
HIFWR_
ISON
93
LINKON
92
LPS
91
LREQ
87
PD
48
PHYCTL0
86
HIFD14
2
HIFD15
1
HIFD8
10
HIFD9
9
HIFINT_
38
HIFMUX
46
40
HIFRD_
36
HIFSC_
HIFAD5
15
HIFAD6
14
HIFAD7
13
HIFALE
39
HIFD10
8
HIFD11
7
HIFD12
4
HIFD13
3
HIFA6
27
HIFA7
26
HIFA8
25
HIFAD0
22
HIFAD1
21
HIFAD2
20
HIFAD3
19
HIFAD4
16
60
69
HIF16BIT
45
HIFA0
33
HIFA1
32
HIFA2
31
HIFA3
30
HIFA4
29
HIFA5
28
112
119
131
137
11
17
23
34
43
53
127
CLK50
55
CYCLEIN
56
CYCLEOUT
57
5
77
83
89
94
106
AV2D7
AV2ENDPCK
123
AV2ERR0|LTLEND
121
122
AV2ERR1|DATINV
AV2FSYNC
125
AV2READY
143
AV2SY
126
AV2SYNC
128
AV2VALID
AV2CLK
AV2D0
133
AV2D1
134
AV2D2
135
AV2D3
136
AV2D4
139
AV2D5
140
AV2D6
141
142
98
96
AV1ERR0
AV1ERR1
97
AV1FSYNC
100
AV1READY
118
AV1SY
101
AV1SYNC
103
AV1VALID
102
124
108
109
AV1D1
AV1D2
110
AV1D3
111
AV1D4
114
AV1D5
115
AV1D6
116
AV1D7
117
AV1ENDPCK
AND
STATUS
CONTROL
REGISTERS
AND
ASYNC
RECEIVER
8-BIT
TRANSMITTER
MEMORY
PACKETS
12KB BUFFER
INTERFACE
ISOCH & ASYNC
TRANSMITTER / RECEIVER
AV2
TRANSMITTER / RECEIVER
AV1
1394MODE
47
AV1CLK
99
AV1D0
PDI1394L40
7201
PDI1394L40
LINK
CORE
4K7
3265
22K
3257
I222
33R
3229
3266
4K7
4201
I200
100n
2226
3208
10K
3281
10K
3230
10K
I206
F1202
3241
3264
4K7
33R
4205
F215
12p
2202
4K7
3263
I207
2220
100n
100R
3271
3210
33R
I212
100n
2224
3225
10R
2201
F1201
270p
56R
3212
3316
100R
3299
3317
100R
100R
I225
100n
2222
100n
2206
3252
33R
F212
F213
4K7
3289
3248
10R
100R
3202
3223
10R
3216
10R
4K7
3256
24M576
1201
CX-11F
3291
4K7
56R
3233
3206
100n
2219
10K
5203
33R
3214
I213
5204
F1205
4
5
6
7
8
1203
SR
1
2
3
I208
1K0
3276
3294
100R
3295
100R
F201
100R
3296
I203
I227
3204
10K
100n
2230
100n
2215
100n
2210
5200
+3V3_LINK
MPIO2_1394_IRQn
I202
MPIO23_1394_LED
PCI_AD(31:0)
PCI_AD(0)
PCI_AD(1)
L_SYNC
L_CLK
L_D_CTL
MPIO9_BOARD_ID_0
MPIO10_BOARD_ID_1
MPIO11_BOARD_ID_2
MPIO12_BOARD_ID_3
MPIO21_1394_POWERDOWN
+3V3_IEEE_D
MPIO8_1394_CNA
PCI_AD(31:0)
+3V3_IEEE_D
+3V3_IEEE_PLL
+3V3_IEEE_A
+3V3
L_D(2)
L_FSYNC
L_VAL
+3V3_LINK
AV1SY
AV1ENDPCK
+5V
MX_D_CTL
+3V3_LINK
RESET_1394n
+3V3_LINK
+3V3_IEEE_D
MX_D(0)
MX_D(1)
MX_D(2)
MX_D(3)
MX_D(4)
MX_D(5)
MX_D(6)
MX_D(7)
MX_D(7:0)
MX_VAL
MX_SYNC
MX_CLK
L_D(7)
L_D(6)
L_D(5)
L_D(4)
L_D(3)
L_D(1)
L_D(0)
+3V3_LINK
AV2ENDPCK
AV2FSYNC
+3V3_IEEE_D
+3V3_IEEE_D
+3V3_IEEE_PLL
+3V3_LINK
L_D(7:0)
+3V3_IEEE_A
+3V3_IEEE_D
+3V3_IEEE_D
+3V3_LINK
+3V3_LINK
+3V3
+3V3
PCI_AD(6)
PCI_AD(7)
PCI_AD(8)
+3V3_LINK
PCI_CBE(1)
PCI_CBE(2)
XIO_SEL1
PCI_AD(24)
PCI_AD(25)
PCI_AD(26)
PCI_AD(27)
PCI_AD(28)
PCI_AD(29)
PCI_AD(30)
PCI_AD(31)
+3V3_LINK
PCI_AD(2)
PCI_AD(3)
PCI_AD(4)
PCI_AD(5)
1.5V
1.7V
TR 09004_001
070403
A: DC, 1 V/Div, 20ns/Div
IC7200 pin 60, F203
Summary of Contents for DRX-2
Page 105: ...DRX 2 DRX 2 105 3 6 Video routing Video IO Europe ...
Page 109: ...DRX 2 DRX 2 109 4 4 Video routing Video IO NAFTA ...
Page 119: ...DRX 2 DRX 2 119 IC DATA Display Board IC7103 TMP87CH74F ...
Page 120: ...DRX 2 DRX 2 120 IC7103 TMP87CH74F ...
Page 121: ...DRX 2 DRX 2 121 IC7103 TMP87CH74F ...
Page 132: ...DRX 2 132 PRINTED CIRCUIT BOARD FRONT DISPLAY P C B Part 1 Bottom View ...
Page 133: ...DRX 2 133 PRINTED CIRCUIT BOARD FRONT DISPLAY P C B Part 2 Bottom View ...
Page 135: ...DRX 2 135 Part 1 Part 2 PRINTED CIRCUIT BOARD U A models ANALOG P C B Bottom View ...
Page 136: ...DRX 2 136 PRINTED CIRCUIT BOARD U A models ANALOG P C B Part 1 Bottom View ...
Page 137: ...DRX 2 137 PRINTED CIRCUIT BOARD ANALOG P C B Part 2 Bottom View U A models ...
Page 139: ...DRX 2 139 Part 1 Part 2 PRINTED CIRCUIT BOARD G model ANALOG P C B Bottom View ...
Page 140: ...DRX 2 140 PRINTED CIRCUIT BOARD G model ANALOG P C B Part 1 Bottom View ...
Page 141: ...DRX 2 141 PRINTED CIRCUIT BOARD ANALOG P C B Part 2 Bottom View G model ...
Page 190: ...DRX 2 ...