Yamaha EMX66M Service Manual Download

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EMX66M

LSI PIN DESCRIPTION

PIN
No.

NAME

I/O

FUNCTION

PIN
No.

NAME

I/O

FUNCTION

1
2
3
4
5
6
7
8
9

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

54
55
56
57
58

59
60
61
62

63
64
65
66
67
68
69
70

71
72
73
74
75
76
77
78
79

81
82
83
84
85
86
87
88
89

91
92
93
94
95
96
97
98
99

100

ED2
ED3
ED4
ED5
ED6
ED7
VSS

VDD

CLKM0
CLKM1

TMS

TDI

TCK

CLKIN

VSS

VDD

CLKO

EA12/ED8
EA13/ED9
EA14/ED10
EA15/ED11

VSS

VDD

EA16/ED12
EA17/ED13
EA18/ES14
EA19/ED15
EA4/ED16
EA5/ED17
EA6/ED18
EA7/ED19

VSS

VDD

EA8/ED20
EA9/ED21
EA10/ED22
EA11/ED23

TEST0
TEST1
TEST2
TEST3

/BIO

/INT1

ARBC1
ARBC2

AX1
AX2
AX3

VSS

VDD

HX/SDA
/EMPTY

AXLR2

AR1
AR2

HRBCK/SA0

HR/SA1

HRS/SA2

VSS

VDD

HXBCK/SCL
HXS/SA3

/CS/SA4

HBCKS/SA5

I2CSEL

VSS

VDD

AXBC1
AXBC2

AXLR1

DIVS

/LAV

/LMV

/DRDY

EMU0
EMU1

TDO

DIV512

ARLR1

ARLR2

HDIR/SA6
SEL5V3V

/MUTE

/TRST

/RS

VSS

VDD

/IOE

/RAS/SRCS

/CAS/SROE

/ROME

/WE
EA0
EA1
EA2
EA3

VSS

VDD

ED0
ED1

I/O
I/O
I/O
I/O
I/O
I/O

S
S

I
I

I
I
I
I

S
S

I/O
I/O
I/O
I/O

S
S

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

S
S

I/O
I/O
I/O
I/O

I
I
I
I
I
I
I
I

O
O
O

S
S

I/O/Z

O/Z

I
I
I
I
I

S
S

I
I

I
I
I

S
S

I
I
I

O
O
O

O/Z

I/O/Z
I/O/Z

O/Z

I
I
I
I
I

S
S

O
O

O
O
O
O
O
O

S
S

I/O
I/O

ZFX-2 (XY297A00) CPU

DSP-ZFX: IC306

External Memory and I/O Data Bus

Ground
Power Supply
Clock Mode

TAP(Test Access Port) Mode Select
TAP Data Input
TAP Clock
Master Clock
Ground
Power Supply
Machine Clock Output

External SRAM and ROM Address Bus/
External DRAM and I/O Data Bus

Ground
Power Supply

External SRAM and ROM Address Bus/
External DRAM and I/O Data Bus


External Memory Address Bus/ External I/O
Data Bus

Ground
Power Supply

External Memory Address Bus/ External I/O
Data Bus

Test Mode Control

Separate Control Input
Interrupt 1
Audio Data Receive Unit 1 bit Clock
Audio Data Receive Unit 2 bit Clock
Audio Data Transmitt Unit 1 Data Output
Audio Data Transmitt Unit 2 Data Output
Audio Data Transmitt Unit 3 Data Output
Ground
Power Supply
Host Interface Data Output/I2C Bus Data
CMEM Update Buffer and HR Resistor Empty Flag Output

Audio Data Transmitt Unit 2/3 Left and
Right Channel Frame Frequency Signal
Audio Data Receive Unit 1 Data Input
Audio Data Receive Unit 2 Data Input
Host Interface Receive Clock / I2C Bus Address 0
Host Interface Data Input/ I2C Bus Address 1
H o s t   I n t e r f a c e   R e c e i v e   D a t a   F r a m e
Frequency Signal/ I2C Bus Address 2
Ground
Power Supply
Host Interface Transmitt Clock/ I2C Bus Clock
H o s t   I n t e r f a c e   T r a n s m i t t   D a t a   F r a m e
Frequency Signal/ I2C Bus Address 3
Host Interface Chip Select/ I2C Bus Address 4
HRBCK/HXBCK Active Edge Select/ I2C Bus Address 5
Host Interface Mode Select
Ground
Power Supply
Audio Data Transmitt Unit 1 bit Clock
Audio Data Transmitt Unit 2/3 bit Click
Audio Data Transmitt Unit 1 Left and Right
Channel Frame Frequency Signal
Machine Clock Output then 8 min.
Ruch ALU Overflow Frag Output
Ruch MAC Overflow Frag Output
Host Interface Transmitt Data Ready Frag Output
Emurator Interrupt 0
Emurator Interrupt 1
TAP(Test Access Port) Data Output
Machine Clock then512 min.
Audio Data Receive Unit 1 Left and Right
Channel Frame Frequency Signal
Audio Data Receive Unit 2 Left and Right
Channel Frame Frequency Signal
Host Interface Data Format Select/ I2C Bus Address 6
Input Level Control
Mute Control
TAP(Test Access Port) Reset
Hardware Reset
Ground
Power Supply
External I/O Enable
External DRAM Low Address Strove/External
SRAM Chip Select
External DRAM Culumn Address Strove/External
SRAM Output Enable
External ROM Enable
External Memory and I/O Wright Enable