67
MOTIF XS6/MOTIF XS7/MOTIF XS8
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
OUTER
NO.
L1
L2
L3
L4
L9
L10
L11
L12
L17
L18
L19
L20
M1
M2
M3
M4
M9
M10
M11
M12
M17
M18
M19
M20
N1
N2
N3
N4
N17
N18
N19
N20
P1
P2
P3
P4
P17
P18
P19
P20
R1
R2
R3
R4
R17
R18
R19
R20
T1
T2
T3
T4
T17
T18
T19
T20
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
A9
A10
A11
A12
VSS3OP
VSS3OP
VSS3OP
VSS3OP
VDD3OP
HPX3
PLL_1V8 (HPLL1)
HPX2
A13
A14
A15
A16
VSS3OP
VSS3OP
VSS3OP
VSS3OP
FILTER_HPLL2
PLL_GND (HPLL1)
PLL_BULK (HPLL1)
FILTER_HPLL1
A17
A18
A19
VSS3OP
VSS3OP
PLL_GND (HPLL2)
PLL_BULK (HPLL2)
PLL_1V8 (HPLL2)
A20/CS7/EN1_A
A21/CS6/EN1_B
A23/CS4/EN2_B/GPO6
CLKO
VSS3I
PLL_BULK (CLK_CBL)
PLL_1V8 (CLK_DBL)
FILTER_CLK_DBL
A22/CS5/EN2_A
VSS3I
GPIO1/CLKE
VDD3OP
VDD3OP
XTAL1
VDD1IH
PLL_GND (CLK_DBL)
VDD1IH
RAS
SDRAM_WE
SDRAM_DQM1
DSAI_TX0
DSAI_TX3
VDD3OP
XTAL2
CAS
CS1
SDRAM_BNK0
VSS3OP
PHD5
VDD3OP
PHLP
VSS3OP
VD5/TDF_IFS0/U1_DSR/HFS1
VDD3OP
GPIO15/WCKO/TDF_OEM/U0_OUT2
FILTER_TDIF
O
O
O
O
–
–
–
–
–
I/O
–
O
O
O
O
O
–
–
–
–
A
–
–
A
O
O
O
–
–
–
–
–
I/O
I/O
I/O
O
–
–
–
A
I/O
–
I/O
–
–
I
–
–
–
O
O
O
O
O
–
O
O
O
O
–
I/O
–
O
–
I/O
–
I/O
A
Address bus
I/O ground
I/O 3.3V
GPIO
PLL 1.8V
GPIO(Z)
Address bus
I/O ground
JETPLL filter component connection
PLL ground
PLL bulk bias
JETPLL filter component connection
Address bus
I/O ground
PLL ground
PLL bulk bias
PLL 1.8V
Address bus / Chip select / Rotary encoder input
Address bus / Chip select / Rotary encoder input / General purpose
SDRAM interface AHB Bus clock
Core ground
PLL bulk bias
PLL 1.8V
Clock Doubler VCO filter component connection
Address bus / Chip select / Rotary encoder input
Core ground
General purpose I/O / SDRAM interface Clock enable
I/O 3.3V
XTAL for clock doubler/power manager/LLC
Core 1.8V
PLL ground
Core 1.8V
SDRAM interface Row address strobe
SDRAM interface Write enable
SDRAM interface Upper byte mask
DSAI Transmitter 0 data line
DSAI Transmitter 3 data line
I/O 3.3V
XTAL for clock doubler/power manager/LLC
SDRAM interface Column address strobe
Chip select
SDRAM interface Bank addsess
I/O ground
PHY tristable data line bit 5
I/O 3.3V
Link power status. Pulsing if isolation barrier present.
I/O ground
Video interface - Data byte bit 5 / TDIF sample rate 0 input / Data set ready UART status input / 512fs base rate clock
I/O 3.3V
General purpose I/O / Word clock out / TDIF emphasis output / UART control programmable output 2 output
TDIF Receiver VCO filter component connection
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
OUTER
NO.
U13
U14
U15
U16
U17
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
VSS3OP
AES_RX2
VDD3OP
DSAI_RX1
VSS3OP
DSAI_SYNCD
DSAI_CKD
DSAI_TX2
SDRAM_DQM0
SDRAM_BNK1
EN3_B/GPIO3/SDRAM_BNK3
PHD4
PHCT0
PHLR
VDD1IH
VD2/TDF_I2/U0_DCD
VD6/TDF_IFS1/U1_DCD/HFS2
VCLK/TDF_O2/U1_OUT1
GPIO14/WCKI/TDF_OFS1/U0_OUT1
PLL_1V8 (AES,ADAT,TDIF)
PLL_GND (AES,ADAT,TDIF)
EXT_512BR
AES_RX3
AES_TX2
DSAI_RX2
DSAI_SYNCA
DSAI_SYNCC
DSAI_TX1
EN3_A /GPIO2/SDRAM_BNK2
SCLK
PHD1
PHD3
PHCT1
PHLO
VD0/TDF_I0/U0_CTS
VD3/TDF_I3/U0_RI
VD7/TDF_IEM/U1_RI
VRDY/TDF_O1/U1_RTS
GPIO13/BLKS/TDF_OFS0/U0_RTS
VSS3I
FILTER_AES
OPTI
AES_RX0
AES_TX0
AES_TX3
DSAI_RX3
DSAI_CKB
DSAI_CKC
PHD0
PHD2
PHD6
PHD7
PHDI
VSS3I
VD1/TDF_I1/U0_DSR
VD4/TDF_ILR/U1_CTS
VFSYNC/TDF_O0/U1_DTS
VEND_DB/TDF_O3/U1_OUT2
VVALID/TDF_OLR/U0_DTS
VDD1IH
FILTER_ADAT
OPTP
EXT_FBR
AES_RX1
AES_TX1
DSAI_RX0
DSAI_CKA
DSAI_SYNCB
–
I
–
I
–
I/O
I/O
O
O
O
I/O
I/O
I/O
O
–
I/O
I/O
I/O
I/O
–
–
I/O
I
O
I
I/O
I/O
O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
–
A
I
I
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I
–
I/O
I/O
I/O
I/O
I/O
–
A
O
I/O
1
O
I
I/O
I/O
I/O ground
AES3 Receiver ch4/5
I/O 3.3V
DSAI Receiver 1 data line
I/O ground
DSAI Sync D
DSAI Clock D
DSAI Transmitter 2 data line
SDRAM interface Lower byte mask
SDRAM interface Bank addsess
Rotary encoder input / General purpose I/O / SDRAM interface Bank addsess
PHY tristable data line bit 4
PHY tristable control line bit 0
Serial request output from S-LINK(Z)
Core 1.8V
Video interface - Data byte bit 2 / TDIF audio data input 3 / Data carrier detect UART status input
Video interface - Data byte bit 6 / TDIF sample rate 1 input / Data carrier detect UART status input / 512fs base rate clock
Video interface - Video Clock / TDIF audio data output 3 / UART control programmable output 1 output
General purpose I/O / Word clock in / TDIF sample rate 1 output / UART control programmable output 1 output
PLL 1.8V
PLL ground
External 512 x base rate clock
AES3 Receiver ch.6/7
AES3 Transmitter ch.4/5
DSAI Receiver 2 data line
DSAI Sync A
DSAI Sync C
DSAI Transmitter 1 data line
Rotary encoder input / General purpose I/O / SDRAM interface Bank addsess
49.152MHz PHY Clock input
PHY tristable data line bit 1
PHY tristable data line bit 3
PHY tristable control line bit 1
Link on indication from PHY. Pulsing when asserted.
Video interface - Data byte bit 0 / TDIF audio data input 1 / Clear to send UART status input
Video interface - Data byte bit 3 / TDIF audio data input 4 / Ring indicator UART status input
Video interface - Data byte bit 7 / TDIF emphasis input / Ring indicator UART status input
Video interface - Video ready signal / TDIF audio data output 2 / UART control request to send output
General purpose I/O / Block sync input/output signal / TDIF sample rate 0 output / UART control request to send output
Core ground
AES Receiver filter component connection
Optical audio in
AES3 Receiver ch.0/1
AES3 Transmitter ch.0/1
AES3 Transmitter ch.6/7
DSAI Receiver 3 data line
DSAI Clock B
DSAI Clock C
PHY tristable data line bit 0
PHY tristable data line bit 2
PHY tristable data line bit 6
PHY tristable data line bit 7
A high indicates isolation barrier is not present.
Core ground
Video interface - Data byte bit 1 / TDIF audio data input 2 / Data set ready UART status input
Video interface - Data byte bit 4 / TDIF left right clock input / Clear to send UART status input
Video interface - Video sync signal / TDIF audio data output 1 / UART control data terminalready output
Video interface - End of Data block / TDIF audio data output 4 / UART control programmable output 1 output
Video interface - Video data valid / TDIF left right clock output / UART control data terminal ready output
Core 1.8V
ADAT Receiver filter component connection
Optical audio out
External 1fs base rate clock
AES3 Receiver ch.2/3
AES3 Transmitter ch.2/3
DSAI Receiver 0 data line
DSAI Clock A
DSAI Sync B