MOTIF XS6/MOTIF XS7/MOTIF XS8
74
IC BLOCK DIAGRAM
(
IC
ブロック図)
1
2
3
1A
1Y
4
2A
5
2B
6
2Y
7
GND
1B
14
13
12
Vcc
4A
11
4Y
10
3B
9
3A
8
3Y
4B
SN74AHCT04PWR
(X4525A00)
SN74AHC04PWR
(X4129A00)
Hex Inverter
HD74LVC08TELL
(X4961A00)
MLAN (XS-8 only): IC115,116,125,126
SN74LVC1G08DCKR
(X5896A00)
Quad 2 Input AND
TC74VHC14FT(EL,K)
(XV890B00)
Hex Inverter
HD74LV21ATELL
(X0010A00)
SN74LV21APWR
(X2377A00)
Dual 4 Input AND
TC74VHCT32AFT-EL
(XZ372A00)
Quad 2 Input OR
TC74LCX74FT(EL,K)
(X8099A00)
SN74LVC74APWR
(X5731A00)
MLAN (XS-8 only): IC113,114,117
Dual D-Type Flip-Flop
HD74LV125ATELL
(X5214A00)
Quad 3-State Bus Buffer
HD74LVC139TELL-E
(X4963A00)
Dual 2 to 4 Demultiplexer
HD74LVC244ATELL
(X2308A00)
Octal 3-State Bus Buffer
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
Vss
14
13
12
11
10
9
8
VDD
6A
6Y
5A
5Y
4A
4Y
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
14
13
12
11
10
9
8
VDD
6A
6Y
5A
5Y
4A
4Y
1
2
3
1A
1Y
4
2A
5
2B
6
2Y
7
VSS
1B
14
13
12
VDD
4A
11
4Y
10
3B
9
3A
8
3Y
4B
1
2
3
1A
NC
4
1C
5
1D
6
1Y
7
GND
1B
14
13
12
Vcc
2C
11
NC
10
2B
9
2A
8
2Y
2D
INPUTS
OUTPUTS
PR
CLR
CLK
D
Q
Q
L
H
H
L
H
Q
O
H
L
H
H
L
Q
O
X
X
X
H
L
X
X
X
X
f
f
L
H
L
L
H
H
H
L
H
L
H
H
H
1
2
3
4
5
6
7
1CLR
1D
1CK
1PR
1Q
1Q
GND
14
13
12
11
10
9
8
VCC
2CLR
CLR
2D
D
2CK
CK
2PR
PR
2Q
2Q
Q
Q
CLR
D
CK
PR
Q
Q
1
2
3
4
5
6
7
C1
A1
Y1
C2
A2
Y2
GND
14
13
12
11
10
9
8
Vcc
C4
A4
Y4
C3
A3
Y3
1
2
3
4
5
6
7
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
A
G
B
Y0
Y1
Y2
Y3
16
15
14
13
12
11
10
Vcc
2G
2A
2B
2Y0
2Y1
2Y2
8
GND
9
2Y3
Y2
Y3
Y1
Y0
B
A
G
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VDD (Vcc)
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
(GND) Vss