A
1
2
3
4
5
6
7
8
9
10
B
C
D
E
F
G
H
I
J
K
L
M
N
105
DIGITAL 3/5
RX-V475/HTR-4066/RX-V500D
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
● ⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更することがあります。
DIGITAL IN
3.3
3.3
1.8
1.2
5.0
5.5
E M D 1 1
E M D 7
E M A 7
N _ E M C S 0
H D M I _ S P F / D L 2
E M D 1 2
E M A 1 4
E M D 4
H D M I _ S D 2 / D L 1
N _ E M C S 2
E M A 4
E M C K E
E M D 1 3
E M A 1 6
H D M I _ S D 3 / D R 2
EMDQM1
E M D 9
E M A 1 5
N _ E M O E
T I _ S D C
H D M I _ S D 1 / D R 1
N _ E M O E
DSP_SCK
EMCLK
T I _ S D F
E M A 9
E M D 2
H D M I _ W C K / D R 0
E M A 4
E M D 6
T I _ B C K
E M A 3
E M D 9
E M A 1 0
E M C L K
T D O
T I _ W C K
TI_SDC
E M A 0
E M A 3
E M A 1 1
E M A 1 0
E M A 6
TCK
E M D 0
E M A 0
E M A 1 2
E M A 1 8
N _ E M C S 2
TDI
TI_SDF
E M D 1 4
E M A 1 4
TI_SDS
N _ E M W E
E M A 1 8
E M A 6
D I R _ B C K
E M D 1 4
TDO
E M A 7
E M B A 0
E M A 0
D I R _ M C K 1
E M A 1 5
E M A 1
D S P _ N _ R S T
N _ E M U 0
SOMI
TI_BCK
DSP_N_CS
N_EMU0
HDMI_WCK/DR0
E M A 5
TI_WCK
E M A 5
E M D 8
D I R _ 2 4 M
D I R _ 2 4 M
E M D 1 0
E M A 6
E M D Q M 1
N _ T R S T
N_EMU1
HDMI_SPF/DL2
DSP_FMT
E M B A 1
E M D 1 1
E M D 3
E M A 1 7
E M A 8
E M A 2
E M A 1 1
E M D 1 0
DIR_MCK1
T I _ S D S B
E M A 1 2
E M D 4
E M D 1
N _ E M R A S
HDMI_SD3/DR2
DSP_N_RDY
D S P _ M I S O
E M B A 1
E M B A 1
T I _ S D S
E M D 5
DIR_WCK
E M D 6
HDMI_SD2/DL1
D S P _ M O S I
T M S
E M D 1
E M A 1 7
D S P _ S C K
DIR_BCK
HDMI_SD1/DR1
DSP_MOSI
N _ E M U 1
D S P _ N _ C S
E M D 1 2
DIR_SDO
E M D 8
EMCKE
E M D 7
E M A 1 3
D S P _ F M T
E M D 5
AUP_SD0
RDY
D I R _ S D O
E M A 1 3
E M A 1 6
D I R _ W C K
A U P _ W C K
DSP_N_INT
E M D 1 5
A U P _ B C K
A U P _ S D 0
DSP_MISO
E M A 9
T D I
N _ E M W E
E M A 8
E M A 1
E M D 3
E M A 2
D S P _ N _ R D Y
E M A 1 0
TMS
E M B A 0
E M D 1 5
D S P _ N _ I N T
AUP_WCK
E M D 2
E M D 1 3
E M D 0
T C K
E M A 3
D S P _ N _ R S T
N_TRST
AUP_BCK
TI_SDSB
E M D Q M 0
N _ E M C A S
N _ E M R A S
N _ E M C S 0
E M A 4
E M A 5
E M A 1
E M A 2
E M A 7
E M A 8
E M A 9
E M A 1 1
N_EMCAS
N_EMWE
EMDQM0
EMD7
EMD6
EMD5
EMD4
EMD3
EMD2
EMD1
EMD0
EMD15
EMD14
EMD13
EMD12
EMD11
EMD10
EMD9
EMD8
+ 1 . 2 D S P
C413
0.1/10(BJ)
C411
0.1/10(BJ)
T I _ B C K
C 4 0 9
0 . 1 / 1 0 ( B J )
C 4 2 8
0 . 1 / 1 0 ( B J )
V C C
D Q 0
V C C Q
D Q 1
D Q 2
V S S Q
D Q 3
D Q 4
V C C Q
D Q 5
D Q 6
V S S Q
D Q 7
V C C
D Q M L
W E
C A S
R A S
C S
A 1 3 / B A 0
A 1 2 / B A 1
A 1 0 / A P
A 0
A 1
A 6
A 7
A 8
A 9
A 1 1
N C
C K E
C L K
D Q M U
N C
V S S
D Q 8
V C C Q
D Q 9
D Q 1 0
V S S Q
D Q 1 1
D Q 1 2
V C C Q
D Q 1 3
D Q 1 4
V S S Q
D Q 1 5
V S S
A 2
V C C
V S S
A 5
A 3
A 4
C 4 0 5
0 . 1 / 1 0 ( B J )
H D M I _ S D 3 / D R 2
D I R _ M C K 1
C 4 2 2
0 . 1 / 1 0 ( B J )
C431
10/6.3
R412
47
+ 3 . 3 D S P 1
R407
4.7K
C 4 0 1
1 0 0 P ( C H )
D S P _ N _ R D Y
D S P _ M I S O
T I _ S D S
C 4 3 2
1 0 0 0 P ( B )
C419
0.1/10(BJ)
C402
1 0 / 6 . 3
D G N D
R 5 0 1
1 0 0 X 4
R415
4.7K
C420
0.1/10(BJ)
D S P _ S C K
C414
0.1/10(BJ)
D S P _ N _ C S
H D M I _ W C K / D R 0
C 4 0 6
0 . 1 / 1 0 ( B J )
+ 3 . 3 D S P
R413
47
T I _ S D F
C417
0.1/10(BJ)
D G N D
L402
BLM21PG600SN1D
C415
0.1/10(BJ)
R 4 1 6
4 . 7 K
C 4 3 7
0 . 1 / 1 0 ( B J )
L403
BKP1005HS680-T
C 4 4 8
0.1/10(BJ)
C418
0.1/10(BJ)
C412
0.1/10(BJ)
R 5 1 6
3 3 X 4
A U P _ B C K
R 4 0 1
1 0 0
D I R _ B C K
C 4 0 7
0 . 1 / 1 0 ( B J )
R 4 0 3
0
D S P _ F M T
V S S
A H C L K X 0 / A H C L K X 2
A M U T E 0
A M U T E 1
A H C L K X 1
V S S
A C L K X 1
C V D D
A C L K R 1
D V D D
A F S X 1
A F S R 1
V S S
R E S E T
V S S
C V D D
C L K I N
V S S
T M S
C V D D
T R S T
O S C V S S
O S C I N
O S C O U T
O S C V D D
EM_CAS
EM_WE
EM_WE_DQM[0
]
VSS
EM_D[7
]
DVDD
EM_D[6
]
CVDD
EM_D[5
]
EM_D[4
]
VSS
EM_D[3]
EM_D[2
]
DVD
D
EM_D[1]
EM_D[0]
CVDD
VSS
EM_D[15]
EM_D[14]
CVD
D
EM_D[13
]
EM_D[12
]
DVD
D
EM_D[11
]
E M _ A [ 4 ]
C V D D
E M _ A [ 3 ]
V S S
E M _ A [ 2 ]
E M _ A [ 1 ]
C V D D
E M _ A [ 0 ]
D V D D
E M _ A [ 1 0 ]
E M _ B A [ 1 ]
V S S
E M _ B A [ 0 ]
E M _ C S [ 0 ]
E M _ R A S
V S S
E M _ C S [ 2 ]
C V D D
E M _ R W
D V D D
E M _ O E
S P I O _ E N A / I 2 C 1 _ S D A
V S S
S P I O _ S C S / I 2 C 1 _ S C L
S P I O _ C L K / I 2 C 0 _ S C L
AXR0[5]/SPI1_SC
S
AXR0[6]/SPI1_EN
A
AXR0[7]/SPI1_CL
K
CVD
D
VSS
DVD
D
AXR0[8]/AXR1[5]/SPI1_SOM
I
AXR0[9]/AXR1[4]/SPI1_SIM
O
CVD
D
VS
S
AXR0[10]/AXR1[3
]
AXR0[11]/AXR1[2
]
CVD
D
VSS
AXR0[12]/AXR1[1
]
AXR0[13]/AXR1[0
]
DVDD
AXR0[14]/AXR2[1
]
AXR0[15]/AXR2[0
]
ACLKR
0
VSS
AFSR
0
ACLKX
0
AHCLKR0/AHCLKR
1
AFSX
0
V S S
P L L H V
T D I
T D O
V S S
D V D D
VSS
EM_D[10]
EM_D[9]
CVDD
EM_D[8]
EM_WE_DQM[1]
DVDD
AXR0[0]
VSS
AXR0[1]
AXR0[2]
AXR0[3]
VSS
AXR0[4]
E M U [ 0 ]
C V D D
V S S
E M _ A [ 7 ]
E M _ A [ 6 ]
D V D D
V S S
E M _ A [ 5 ]
C V D D
E M U [ 1 ]
T C K
V S S
VSS
EM_CLK
EM_CKE
VSS
E M _ A [ 8 ]
D V D D
E M _ A [ 1 1 ]
E M _ A [ 9 ]
DVDD
VS
S
SPIO_SIMO
SPIO_SOMI/I2C0_SD
A
C 4 4 2
0 . 1 / 1 0 ( B J )
D G N D
C403
0 . 1 / 1 0 ( B J )
A U P _ W C K
R410
47
C 4 3 0
1 0 0 0 P ( B )
A U P _ S D 0
C429
0.1/10(BJ)
R419
47
C410
0.1/10(BJ)
C 4 5 6
0 . 1 / 1 0 ( B J )
R 4 0 2
n o _ u s e
D S P _ N _ I N T
D G N D
R 4 0 4
1 0 0
R 4 2 3
4 . 7 K
H D M I _ S D 2 / D L 1
R 4 0 5
1 0 0
+ 3 . 3 D S P 1
C 4 2 5
0 . 1 / 1 0 ( B J )
C 4 5 7
0 . 1 / 1 0 ( B J )
C 4 2 6
0 . 1 / 1 0 ( B J )
H D M I _ S D 1 / D R 1
C416
0.1/10(BJ)
R 5 1 3
3 3 X 4
R 5 1 5
3 3 X 4
T I _ S D S B
D S P _ N _ R S T
D I R _ S D O
R411
47
+ 3 . 3 D S P
+ 3 . 3 D
R 4 0 9
1 0 K
D G N D
L 4 0 1
B K P 1 0 0 5 H S 6 8 0 - T
D S P _ M O S I
R 4 2 2
4 . 7 K
R408
4.7K
D G N D
T I _ S D C
R420
47
T I _ W C K
C 4 4 1
0 . 1 / 1 0 ( B J )
C 4 0 8
0 . 1 / 1 0 ( B J )
C434
10/6.3
D I R _ 2 4 M
C 4 3 5
0 . 1 / 1 0 ( B J )
D G N D
C 4 2 3
0 . 1 / 1 0 ( B J )
R 4 0 6
1 0 0
C421
0.1/10(BJ)
R430
4.7K
I C 4 6
n o _ u s e
R 4 1 8
4 . 7 K
D I R _ W C K
R 4 1 7
4 . 7 K
C 4 2 4
0 . 1 / 1 0 ( B J )
C 4 2 7
0 . 1 / 1 0 ( B J )
C 4 4 7
0 . 1 / 1 0 ( B J )
C 4 3 6
0.1/10(BJ)
C 4 0 4
0 . 1 / 1 0 ( B J )
H D M I _ S P F / D L 2
C433
10/6.3
D G N D
R 5 1 4
3 3 X 4
R414
33
D G N D
R429
4.7K
+ 3 . 3 D S P
+ 3 . 3 D
Q402
DTA044EUBTL
C453
0.01/16(B)
R426
100K
D G N D
R421
no_use
D S P _ P O N
C450
1/25
D G N D
R P 1 3 0 Q 5 0 1 D - T R - F
I C 4 4
VDD
GND
VOUT
CE/CE
T P 2 0 2 0
+ 5 . 5 V
C452
1/25
+ 5 D
L405
BKP1005HS680-T
C454
10/6.3
D
8
.
1
+
C451
10/6.3
D G N D
R 1 1 7 2 H 1 2 1 D - T 1 - F
I C 4 5
CEorCE
GND
NC
VDD
VOUT
+ 1 . 2 D S P
R 5 0 8
4 7 X 4
R503
100X4
D G N D D G N D
D S P _ N _ P O N
R A L 0 3 5 P 0 1
Q 4 0 1
1
2
3
4
5
6
C B 4 1
n o _ u s e
1
2
5
1
6
1
3
4
5
6
7
8
9
1 0 1 1 1 2 1 3 1 4
R 5 0 2
4 . 7 K X 4
1
2
4
5
7
8
3
6
C551
220/16
D Q 1 5
A 9
A 1 4
TMS
A 1 2
D Q 8
A 7
A 1 8
D Q 0
A 1 5
From 001.sht
(HDMI RxTx)
D Q 3
V S S
(DSD DR1)
A 5
D Q 9
TDI
(DSD DL1)
D Q 2
DGND
(DSD DR2)
A 3
A 1 1
(DSD DL2)
N . C .
A 6
I C / C B / X L : 4 1 - 6 0
A r r a y R : 5 0 1 - 6 0 0
P o l e r C : 5 5 1 - 6 0 0
O H T E R : 4 0 1 - 6 0 0
(DSD DR0)
/TRST
/EMU(1)
D Q 1 1
A 4
D I G I T A L 3 : D S P
(DSD CLK)
DGND
D Q 1 4
(DSD DRL0)
A 2
D Q 1 3
TCK_RET
D Q 7
O E
D Q 5
A 1 0
A 1 6
D Q 6
DGND
6 4 M b i t
/EMU(0)
B Y T E
W E
1 6 M b i t
A 1 7
P a r a l l e l F l a s h
F l a s h M e m o r y
R E S E T
V C C
From 002.sht
(CPU)
TDO
From 004.sht
(DIR)
TCK
to 004.sht
(DAC)
A 8
KEY
V S S
D Q 1 0
D S P J T A G
C E
N . C .
S D R A M
A 0
R Y / B Y
DGND
D Q 1
B o o t m o d e :
A 1 9
D Q 4
A 1
D Q 1 2
N . C .
A 1 3
PD(+3.3V)
+ 3 . 3 D S P
V c e h = 1 ~ 6 . 5 V
V c e l = 0 - 0 . 4 V
+ 5 D ( m a i n p c b O P T )
+ 1 . 2 D S P
F r o m 0 0 2 . s h t
( C P U )
T o 0 0 1 . s h t
( H D M I )
M X 2 9 L V 1 6 0 D B T I - 7 0 G
Y F 2 8 0 A 0
X 3 0 4 2 E 0
W r i t t e n b y Y E M
X 8 9 5 0 C 0
E N 2 9 L V 1 6 0 C B - 7 0 T I P
X 9 6 2 5 C 0
X Z 4 1 4 F 0
M 1 2 L 6 4 1 6 4 A - 5 T G 2 Y
W 9 8 6 4 G 6 J H - 6
R E M A R K S
C A P A C I T O R
P A R T S
N A M E
N O
N O
M A R K
M A R K
E L E C T R O L Y T I C
C A P A C I T O R
C E R A M I C
C A P A C I T O R
P O L Y E S T E R F I L M
C A P A C I T O R
P O L Y S T Y R E N E
F I L M
C A P A C I T O R
M I C A
C A P A C I T O R
P O L Y P R O P Y L E N E
F I L M
C A P A C I T O R
S E M I C O N D U C T I V E C E R A M I C C A P A C I T O R
P
T A N T A L U M
C A P A C I T O R
T U B U L A R
S
C A P A C I T O R
C E R A M I C
F I L M
S U L F I D E
P O L Y P H E N Y L E N E
C A P A C I T O R
R E S I S T O R
R E M A R K S
N O M A R K
P A R T S
N A M E
C A R B O N
C A R B O N
M E T A L
M E T A L
M E T A L
F I R E
C E M E N T
S E M I
F I L M
R E S I S T O R
F I L M
R E S I S T O R
O X I D E
F I L M
R E S I S T O R
F I L M
R E S I S T O R
P L A T E
R E S I S T O R
P R O O F C A R B O N
F I L M
R E S I S T O R
M O L D E D
R E S I S T O R
V A R I A B L E
R E S I S T O R
( P = 5 )
( P = 1 0 )
C H I P
R E S I S T O R
N O T I C E
U . S . A
G
C A N A D A
E U R O P E
L
C H I N A
A U S T R A L I A
S I N G A P O R E
K O R E A
G E N E R A L
U
C
T
A
K
R
J A P A N
( m o d e l )
B
B R I T I S H
J
S O U T H E U R O P E
E
V
T A I W A N
F
R U S S I A N
P
L A T I N A M E R I C A
S
B R A Z I L
H
T H A I
IC41:
D70YE101BRFP266
Floating-point digital signal processors
256
256
C67x+ Microprocessor
D1
64
R/W
Data
D2
R/W
Program
Fetch
Memory
Controller
Program/Data
RAM
256K Bytes
JTAG EMU
McASP DMA Bus
Peripheral Configuration Bus
McASP0
16 Serializes
McASP1
6 Serializes
McASP2
2 Serializes
DIT Only
SPI1
SPI0
I2C0
I2C1
RTI
PLL
Program/Data
ROM Page1
256K Bytes
Program/Data
ROM Page2
256K Bytes
Program/Data
ROM Page3
256K Bytes
High-performance
Crossbar Switch
CSP
PMP DMP
Program
Cache
32K Bytes
I/O
I/O
MAX0
MAX1
Events
In
CONTROL
dMAX
EMIF
Peripheral Interrupt and DMA Events
Interrupts
Out
INT
Data
256
256
256
256
32
32
32
32
32
32
32
32
32
32
32
64
32
32
32
32
32
32
32
32
32
32
VDD
A3
A2
A1
A0
A10/AP
A12
A13
CS
RAS
CAS
WE
LDQM
VDD
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDDQ
VDDQ
VSSQ
DQ0
VDD
VSS
A4
A5
A6
A7
A8
A9
A11
NC
CKE
CLK
UDQM
NC
VSS
VDDQ
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSSQ
VSSQ
VDDQ
DQ15
VSS
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
IC42
: M12L64164A-5TG
1M x 16-bit x 4 banks synchronous DRAM
CLK
CS
RAS
CAS
WE
C
ommand Decoder
C
ontr
ol Logic
Latch Cir
cuit
Input and Output
Buf
fe
r
R
o
w Decoder
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
L(U)DQM
DQ
CKE
Address
Clock
Generator
Row
Address
Buffer
Column
Address
Buffer
and
and
Refresh
Counter
Refresh
Counter
Mode
Register
Bank B
Bank C
Bank D
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
RY/BY#
WP#/ACC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
AM: MSB address
A0-AM
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
IC43
: MX29LV160DBTI-70G
16 M-bit 3 V supply flash memory
V
DD
CE
Pin No.
1
2
3
4
5
Symbol
V
OUT
GND
CE
NC
V
DD
Description
Output Pin of Voltage Regulator
Ground Pin
Chip Enable Pin
No Connection
Input Pin
Vref
5
4
2
1
Current Limit
V
OUT
GND
IC45
: R1172H121D-T1-F
CMOS-based positive-voltage regulator IC
V
DD
CE
Vref
4
3
1
2
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V
OUT
GND
CE
V
DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC44
: RP130Q501D-TR-F
Voltage regulator
to DIGITAL 1/5
to DIGITAL 1/5
to DIGITAL 2/5
to DIGITAL 4/5
to DIGITAL 2/5
SDRAM 64 Mbit
FLASH ROM 16 Mbit
No replacement part available.
to DIGITAL 4/5
RX-V475/HTR-4066
RX-V500D
Summary of Contents for RX-V500D
Page 9: ...RX V500D A model RX V500D B G models 9 RX V475 HTR 4066 RX V500D RX V475 HTR 4066 RX V500D ...
Page 132: ... CONFIGURING THE SYSTEM SETTINGS RX V475 HTR 4066 RX V500D 133 ...
Page 133: ... システム設定を変更する RX V475 HTR 4066 RX V500D 134 ...
Page 146: ...147 RX V475 HTR 4066 RX V500D RX V475 HTR 4066 RX V500D MEMO ...
Page 147: ...RX V475 HTR 4066 RX V500D ...