YSP-1100
44
YSP-1100
■
IC DATA
IC26 : M30626FJPFP (DSP P.C.B)
16-bit Microprocessor
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
Memory
ROM
(1)
RAM
(2)
A/D converter
(10 bits
X
8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits
X
3 channels)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P1
8
Port P2
8
8
8
8
Port P6
8
8
R0L
R0H
R1H
R1L
R2
R3
A0
A1
FB
SB
ISP
USP
INTB
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
Multiplier
7
8
8
P
o
rt
P10
Po
rt
P
9
P
o
rt
P8_5
Po
rt
P
8
Po
rt
P
7
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Port P5
Port P4
Port P3
Clock synchronous serial I/O
(8 bits
X
2 channels)
PC
FLG
Timer (16-bit)
Three-phase motor
control circuit
8
8
8
2
Port P11
Port P12
Port P14
Port P13
(3)
<VCC2 ports>
(4)
<VCC1 ports>
(4)
<VCC1 por
ts>
(4)
<VCC2 ports>
(4)
<VCC1 ports>
(4)
(3)
(3)
(3)
1
2 3
4 5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P
1
_
0
/D
8
P
1
_
1
/D
9
P
1
_
2
/D
1
0
P
1
_
3
/D
1
1
P
1
_
4
/D
1
2
VREF
AVSS
V
C
C
1
X
IN
X
O
U
T
V
S
S
R
E
S
E
T
C
N
V
S
S
P
8
_
7
/X
C
IN
P
8
_
6
/X
C
O
U
T
B
Y
T
E
P
2
_
0
/A
N
2
_
0
/A
0
(/D
0
/-)
P
2
_
1
/A
N
2
_
1
/A
1
(/D
1
/D
0
)
P
2
_
2
/A
N
2
_
2
/A
2
(/D
2
/D
1
)
P
2
_
3
/A
N
2
_
3
/A
3
(/D
3
/D
2
)
P
2
_
4
/A
N
2
_
4
/A
4
(/D
4
/D
3
)
P
2
_
5
/A
N
2
_
5
/A
5
(/D
5
/D
4
)
P
2
_
6
/A
N
2
_
6
/A
6
(/D
6
/D
5
)
P
2
_
7
/A
N
2
_
7
/A
7
(/D
7
/D
6
)
P
3
_
0
/A
8
(/-
/D
7
)
P
3
_
1
/A
9
P
3
_
2
/A
1
0
P
3
_
3
/A
1
1
P
3
_
4
/A
1
2
P
3
_
5
/A
1
3
P
3
_
6
/A
1
4
P
3
_
7
/A
1
5
P
4
_
0
/A
1
6
P
4
_
1
/A
1
7
P
4
_
2
/A
1
8
P
4
_
3
/A
1
9
P
7
_
4
/T
A
2
O
U
T
/W
P
7
_
6
/T
A
3
O
U
T
P5_6/ALE
P
7
_
7
/T
A
3
IN
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
V
C
C
2
V
S
S
P5_7/RDY/CLKOUT
P4_5/CS1
P4_6/CS2
P4_7/CS3
AVCC
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P
9
_
3
/D
A
0
/T
B
3
IN
P
9
_
4
/D
A
1
/T
B
4
IN
P
9
_
5
/A
N
E
X
0
/C
L
K
4
P
9
_
6
/A
N
E
X
1
/S
O
U
T
4
P
9
_
1
/T
B
1
IN
/S
IN
3
P
9
_
2
/T
B
2
IN
/S
O
U
T
3
P
8
_
0
/T
A
4
O
U
T
/U
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P
7
_
2
/C
L
K
2
/T
A
1
O
U
T
/V
P
8
_
2
/IN
T
0
P
7
_
1
/R
X
D
2
/S
C
L
2
/T
A
0
IN
/T
B
5
IN
(1
)
P
8
_
3
/IN
T
1
P
8
_
5
/N
M
I
P9_7/ADTRG/SIN4
P4_4/CS0
P5_0/WRL/WR
P5_1/WRH/BHE
P
9
_
0
/T
B
0
IN
/C
L
K
3
P
7
_
0
/T
X
D
2
/S
D
A
2
/T
A
0
O
U
T
(1
)
P
8
_
4
/IN
T
2
/Z
P
P
8
_
1
/T
A
4
IN
/U
P
7
_
3
/C
T
S
2
/R
T
S
2
/T
A
1
IN
/V
P
7
_
5
/T
A
2
IN
/W
P
1
_
5
/D
1
3
/IN
T
3
P
1
_
6
/D
1
4
/IN
T
4
P
1
_
7
/D
1
5
/IN
T
5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
