n
Priority:
Here the priorities may be specified according to which the corresponding cyclic inter-
rupt is processed. With priority "0" the corresponding interrupt is deactivated.
n
Execution:
Enter the time intervals in ms, in which the watchdog interrupt OBs should be pro-
cessed. The start time for the clock is when the operating mode switch is moved from
STOP to RUN.
n
Phase offset:
Enter the delay time in ms for current execution for the watch dog interrupt. This
should be performed if several watchdog interrupts are enabled. Phase offset allows
to distribute processing time for watchdog interrupts across the cycle.
n
Process image partition:
This parameter is not supported.
n
Level of protection:
Here 1 of 3 protection levels may be set to protect the CPU from unauthorized
access.
–
Protection level 1 (default setting):
No password adjustable, no restrictions
–
Protection level 2 with password:
Authorized users: read and write access
Unauthorized user: read access only
–
Protection level 3:
Authorized users: read and write access
Unauthorized user: no read and write access
5.9 Project transfer
There are the following possibilities for project transfer into the CPU:
n
Transfer via MPI
n
Transfer via Ethernet
n
Transfer via memory card
5.9.1 Transfer via MPI
For transfer via MPI there is the following interface:
n
X2: MPI interface
The structure of a MPI net is electrically identical with the structure of a PROFIBUS net.
This means the same rules are valid and you use the same components for the build-up.
The single participants are connected with each other via bus interface plugs and
PROFIBUS cables. Per default the MPI net runs with 187.5kbaud. VIPA CPUs are deliv-
ered with MPI address 2.
The MPI programming cables are available at VIPA in different variants. The cables pro-
vide a RS232 res. USB plug for the PC and a bus enabled RS485 plug for the CPU. Due
to the RS485 connection you may plug the MPI programming cables directly to an
already plugged plug on the RS485 jack. Every bus participant identifies itself at the bus
with an unique address, in the course of the address 0 is reserved for programming
devices.
Cyclic interrupts
Protection
Overview
General
Net structure
MPI programming cable
VIPA System 300S
+
Deployment CPU 313-5BF23
Project transfer > Transfer via MPI
HB140 | CPU-SC | 313-5BF23 | en | 19-01
58