55
CIRCUIT DESCRIPTION
judgment upon these inputs. Then the Microprocessor can us Clock, Data and Enable lines to control the
Tuner. Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20, 21
and 44) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the Clock
and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data
arrive at I014 at pin 2 and pin 3 and are output at pin18 and pin17. They arrive at the Main Tuner at pins (4
and 5). The PinP Tuner doesnt have MTS capability. It only output mono audio, so no switching takes
place for the PinP Tuner U202 audio circuit. The only difference for the PinP tuner control lines is related to
the PinP Enable line. This is output from the Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin
(17). Clock and Data are the same as for the Main Tuner.
Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, and 2, and Tuner 2
(AUX) or In From Converter.
The Remote Control or the Front Panel switches can select the different inputs. This is accomplished by the
INPUT button. Each time the Input button is pressed, the different inputs are sequentially selected. The
sequential order is, Main Tuner, AVX 1, AVX 2, AVX 3, AVX 4, 2nd Antenna and back to Main Tuner. In
addition, if there are S-Inputs on AVX1, 2 or 4, an internal mechanical switch inside the S-Jack tells the
Microprocessor an S-Jack is inserted. Then when that particular input is selected, it automatically selects S
as its source. The same thing holds true for Component inputs. The set should never have Component
inputs and S-Jack inserted at the same time. This will cause a black and white picture will be displayed.
PAGE 02-11
Use this explanation in conjunction with the Microprocessor Data Communications circuit dia-
gram.
The Microprocessor must keep in communication with the Chassis to maintain control over the individual
circuits. Some of the circuits must return information as well so the Microprocessor will know how to
respond to different request. The Microprocessor uses a combination of I 2 C Bus communication and the
Standard Data, Clock and Load lines for control. The I 2 C communication scheme only requires 2 lines for
control. These lines are called SDA and SCL. System Data and System Clock respectively. The Micropro-
cessor also requires the use of what are called Fan Out IC or DACs, (Digital to Analog Converters). This
allows the Microprocessor to us only two lines to control many different circuits. In addition, because this
Microprocessor operates at the new 3.3Vdc voltage, it requires a Level Shift IC to bring up the DC level of
the control lines to make it compatible with the connected ICs. The Microprocessor communicates with the
following ICs:
ON THE SIGNAL PWB:
Main Tuner U201
PinP Tuner U202
EEPROM I002
Flex Converter U205
DAC1 I003
DAC2 I004
Level Shift I014
3D Y/C U204
Main Video Chroma I201
