ZXC10-BTS (V5.4) Installation Manual
7-30
Fig. 7.3-5 Structure of the LINK Cable
Table 7.3-4 IDs of the LINK Directions
Cable Name and Code
To End A
To End B
LINK cable
1#BTS-BBDS4-X70(CLK_MBTS)
1#BTS rack
top-MBDS_SBDS
LINK cable
2#BTS-BBDS4-X70(CLK_SBTS)
2#BTS rack
top-MBDS_SBDS
The LINK cables distribute the IP extension cascade clock and control signals (one for
MBTS output and one for SBTS input) to rack top for cabinet combination purpose.
Definition of signals:
I
_
30M+_MBTS I_30M-_MBTS: The 30M differential MLVDS digital clock
from MBTS_CDM input to the SBTS rack
_MBDS I_CHIP-_MBDS: The 16CHIP differential MLVDS clock
from MBDS_GCM output to RIM of SBDS
I_PP2S
+_
MBDS I
_
PP2S-
_
MBDS: The PP2S differential MLVDS clock from
MBDS_GCM output to RIM of SBDS
2. Clock signal jumpers between racks
The structure of the DB9 clock cable LINK between the basic and extended
racks is shown in Fig. 7.3-6.
Fig. 7.3-6 LINK Cable Structure
The backplane LINK cable of the extended multi-carrier rack is the rack top
jumper.
