Advanced Micro Computers Am96/4116A, User Manual

Page 1: ...Advanced Micro Computers A subsidiary of Advanced Micro Devices Am96 4116A AmZ8000 16 Bit MonoBoard C omputer User s Manual 059910090 001 10 00 ...

Page 2: ...l Released 10101 81 Publication No 059910090 001 Address comments concerning this manual to REVISION l ETTERS I 0 a AND x ARE NOT USED 1981 Advanced Micro Computers Printed in U S A ii ADVANCED MICRO COMPUTERS Publications Department 3340 Scott Boulevard Santa Clara CA 95051 ...

Page 3: ...onfusion and simplify presentation the following convention is used throughout this manual The mnemon ic for a signal that is active low is followed by an asteri sk i e MEM R The mnemon ic for an act i ve h igh signal is denoted without the asterisk suffix Common mnemonics and acronyms are used without additional explanation The fi rst time a non standard or uncommon acronym is used its full name ...

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Page 5: ...3 1 Block Select Memory Expansion 3 2 ROM Addressing o 3 2 Serial I O Interface Programming o 3 4 Am9551 Initialization 3 4 Am9551 Mode Instruction Word Format 3 5 Am9551 Sync Characters 3 5 Command Instruction Word Format 3 5 Am9551 Status Read 3 6 Parallel I O Interface Programming 3 8 Am8255A Addressing 3 8 Am8255A Initialization 3 8 Am8255A Operation Control Word Format 3 11 Am8255A Bit Set Re...

Page 6: ...ty Mode A Automatic Rotation 3 16 3 12 Status Register Bits 3 18 3 13 Master Mode Register Bits 3 20 3 14 Time of Day Configurationo 3 21 3 15 Frequency Scaler Ratios 3 23 3 16 Data Pointer Counter 3 24 vi 3 17 Counter Mode Register Bit Assignments 3 28 3 18 TC Waveform Format 3 29 4 1 Am96 4116A MonoBoard Computer Block Diagram 4 2 4 2 CPU Memory Operations 4 4 4 3 Processor to Processor Transfer...

Page 7: ... Parallel I O Port A and B Jumpers 2 7 2 8 Parallel I O Socket Compatible Line Drivers 2 8 2 9 2 10 2 10 2 11 2 12 3 1 3 2 3 3 3 4 3 5 Parallel I O Connector P3 2 8 ROM Type Jumper Selection 2 9 Am96 4116A Connectors 2 10 System Bus Connector PI Pin Assignments 2 11 Am96 4116A Bus DC Characteristics 2 12 I O Port Address 3 2 Parallel I O Port Configuration Summary 3 9 Control Element Summary 3 17 ...

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Page 9: ...on of RAM RAM can be simul taneous1y accessed by the AmZ8000 and the Multibus If both are attempting continuous access 50 interleave results Eight fully programmable vectored priority interrupt channels wi th provi sions for software generated interrupts 24 sources Two Ser a1 Communi cations Interfaces one wi th full RS232C support and the other with modified RS232C support A parallel I O interfac...

Page 10: ...it word 16 bit and long word 32 bit data types Figure 1 1 is a block diagram of the Am96 4116A Selection of ROM is optional Two sockets are provided to accommodate ROM The ROM type can be Arn2708 or Arn2758 2 ki1obytes Arn2716 or Am9218 4 kilobytes or Arn2732 or Am9233 8 kilobytes Jumpers are provided to select the correct ROM addressing scheme to accommodate the various ROMs Addresses for the Am2...

Page 11: ...L 110 SERIAL 110 CLOCK I t v 8 t v 8 I 8 16 BIT 16 16 ADDRESS r f ADDRESS ADDRESS RESET BUFFER BUFFER t CIRCUITS r I I MULTI AmZ8002 MASTER CONTROL t 16 BIT 16 DATA DATA DATA BUFFER f16 16 16 f8 BUFFER RAM 32K ROM Am9513 8259A BYTES SYSTEM TIMING INTERRUPT DUAL ACCESS 21418 K BYTES CONTROLLER CONTROLLER f8 I I INTERRUPT JUMPER PINS P2 P1 Figure 1 1 Am96 4116A MonoBoard Computer Block Diagram ...

Page 12: ...cted interrupt from interrupt matrix and odd word trap The system contains one Arn8255A Programmable Peripheral Interface containing three parallel I O ports Two 8 bit ports are buffered with bidirectional buffers The buffer direction for each port is selected by jumper to provide either input output or dynamic direction control using a bit from one of the two 4 bit ports The remaining port on the...

Page 13: ... output 1i nes are brought out to connector P2 at the bottom of the board SPECIFICATIONS Specifications for the Am96 4116 MonoBoard Computer are listed in table 1 1 TABLE 1 1 SPECIFICATIONS Word Size Instruct I on Data 1 word 16 bits to 4 words 64 bits byte 8 bits word 16 bits or long word 32 bl ts Memory Addressing On board ROM EPRa 1 Q 7FFH 2708 chips O OFFFH 2716 chips 0 1 FFFH 2732 ch Ips On b...

Page 14: ... Interface Clocks BCLK and CCLK jumperable Exchange Capability Serial priority on board Paral lei pr lorlty off board Bus Lock Wr Ite to I O port FFF9H locks the bus to exclude other access Write to I O port FFF8H un locks the bus Multibus Interrupts Non bus vectored Interrupts are supported and may be Implemented with the following options Interrupts are always j umpered recognized when J L9 Port...

Page 15: ...5 to 8 bi t characters Break character generation 1 1 1 2 or 2 stop bits False start bit detector Programmab Ie Power Requirements En vi ronmenta I Characteristics Paral lei Ity 5V DC 12V DC 12V DC I O Capac Two 8 bl t ports A and B Two 4 bl t ports C even and C odd socketed for drivers or receivers Typical With E PROM devices Instal lad 3 80A 0 10A 0 03A 0 to 55 C up to 90 without condensation Ph...

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Page 17: ...ned If the carri er s agent is not present when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection Shipping damages should be immediately reported to the carrier NOTE Do not attempt to service the board yourself as this will void the warranty It is suggested that salvageable shipping cartons and packing atcrials be saved ...

Page 18: ...2 1 lists the jumpers available TABLE 2 1 MEMORY EXPANSION JUMPERS SIGNAL JUMPER PIN s PCO 10 PCl 12 PC2 14 PC4 16 ADRF 62 63 ADI0 65 36 37 ADll 68 38 39 ADI2 58 40 41 ADI3 59 42 43 N S 66 I FETCH 69 For exampl e to connect PCO to the Mul ti bus ADI0 pi n connect a jumper from pin 10 to 65 and a jumper from 36 to 37 To connect PCl to ADll connect a jumper from 12 to 68 and another from 38 to 39 Tw...

Page 19: ...SS OF ON BOARD RAM On board RAM can be located in ei ther the upper or lower 32K of the Am96 4116 memory space For the upper 32K byte space connect a jumper between pi n 192 and 193 To locate RAM in the lower 32K byte area reconnect the jumper between pi n 192 and 193 To locate RAM in the lower 32K byte area reconnect the jumper between pins 193 and 194 WAIT STATE FOI SLOW ROM One wait state is l ...

Page 20: ...81 179 Ground None CLK 1 Baud Rate Clk 1 141 143 9600 Baud None 142 143 Prog None CLK 2 Baud Rate Clk 2 39 140 9600 Baud None 138 139 Prog None P4 is Serial Port 1 P5 is Serial Port 2 Modified RS232C BAUD RATE SELECT The Am96 4116A baud rate is programmable us i ng two of the counters in the Am9513 System Timing Controller As shipped from the factory the baud rate is set at 9600 Table 2 2 lists th...

Page 21: ...sed 11 9 CLEAR TO SEND 5 22 RX RET RX ClK 24 10 Not Used 18 23 Not Used 12 11 DATA SET READY 6 24 Not Used 25 12 Not Used 19 25 Not Used 13 13 SIGNAL GND 7 26 SIGNAL GND AUXILIARY CONNECTOR P2 Connector P2 is a 60 pi n daub1e s ided edge connector that provi des interface to the Am9513 System Timing Controller Table 2 4 lists the signals and pin numbers for P2 IN SIGNAL 43 GATE3 45 GATE4 47 GATE5 ...

Page 22: ...02 NVI On B INTO Buf On B INT1 Buf On B INT2 Buf On B INT3 Buf On B INT4 Buf On B INT5 Buf On B INT6 Buf On B INT7 Buf On B SIGNAL PIN COLUMN 1 COLUMN 2 NO JUMPER PINS JUMPER PINS INT INPUT oard 98 oard 101 oard 99 oard 100 oard 102 oard 103 oard 118 oard 114 oard 120 oard 116 oard 112 oard 122 78 113 IRC 7 oard 126 81 115 IRQ6 oard 124 84 117 IRQ5 oard 130 87 119 IRQ4 oard 75 129 90 121 IRQ3 oard...

Page 23: ...ted by ei ther a 220n 330n divider or a 1Kn pull up as shown in figure 2 2 The 220n 330n Pull Up Pull DoW n Pack is stocked by di st ri butor under Intel part number SBG 901 and National Semiconductor part number BLC 901 The 1Kn Pull Up Pack is stocked under Intel part number SBC 902 and National Semiconductor part number BLC 902 Table 2 9 lists the pin connections for parallel I O connector P3 TA...

Page 24: ...ABLE 2 9 PARALLEL I O CONNECTOR P3 2 8 PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 SIGNAL PIN SIGNAL PB7 2 Ground PB6 4 Ground PB5 6 Ground Port B PB4 8 Ground PB3 10 Ground PB2 12 Ground PBI 14 Ground PBO 16 Ground PC3 18 Ground PC2 20 Ground PCI 22 Ground Port C PCO 24 Ground PC4 26 Ground PC5 28 Ground PC6 30 Ground PC7 32 Ground PA7 34 Ground PA6 36 Ground PA5 38 ...

Page 25: ...ROM select 177 178 177 178 174 176 174 176 175 176 Note For 2708 types connect 70 to 71 All others 71 to 72 SYSTEM BUS PRIORITY If the Am96 4116A is not the highest priority master jumper pins 22 to 23 Jumper pins 21 to 22 for highest priority Jumper pins 184 and 185 to dri ve BPRO Bus Pri ori ty OUT Jumpers i nsta11 ed at the factory are 22 23 and 184 185 sets up the daisy chain priority scheme I...

Page 26: ...el peripheral interface through P3 and to two serial peripheral interfaces through P4 and P5 Table 2 11 lists the mating connectors TABLE 2 11 Am96 4116A CONNECTORS CONNECTOR NUMBER NUMBER OF PINS PI 86 P2 60 P3 50 P4 26 P5 26 CONNECTOR EQUIVALENT CHARACTERISTICS TYPE 0 156 inch spacing CDC VPB01E43A OOA1 0 100 inch s paci ng 0 100 inch spacing 3M 3415 0001 0 100 inch spacing 3M 3462 0001 0 100 in...

Page 27: ...D SIgla I GND 78 Reserved 80 12 12 VDC 82 5 5 VDC 84 5 5 VDC 86 GND Signal GND ga t edge Canponent Side Pin Mnemon Ic Descr Ipt Ion 1 GND SIgla I GND 3 5 5 VDC Power 5 5 5 VDC Supp lies 7 12 12 VDC 9 5 Not Used 11 GND Signal GND 13 BCLK Bus Clock 15 BPRN Bus Priority In 17 BUSY Bus Busy 19 MRDC Mem Read Canmand Bus 21 ICRC I O Read Command Controls 23 XACK XFER Acknow Iedge 25 AACK Ad vanced Ackn ...

Page 28: ...itive Load Output Low Voltage Output High Voltage Capacitive Load Input Low Voltage Input High Voltage Input Curr ent at Low V Input Current at High V Capaciti V l Load Output Low Voltage Output High Voltage Output Leakage High Output Leakage Low Capacitive Load Output Low Voitage Output High Voltage Input Low Voltage Input High Voltage Input Curl ent at Low V Input Current at High V Capacitive Lo...

Page 29: ...summary of I O addresses is listed in table 3 1 NOTE I O addresses from COOOH to FFFFH are reserved for the Arn96 4116 board SHARED MEMORY AND THE MUI TIBUS Sometimes it is useful for two processors to share the same memory locations in order to communicate and pass data With the Am96 4116A only byte 8 bit operations should be used when passing data between processors and shared memory The Multibu...

Page 30: ...100 0 FFFO Shadow ROM ON Write FFFO 1 1 1 1 100 1 FFFl Shadow ROM OFF Write FFFl BLOCK SELECT MEMORY EXPANSION Norma11y CPU address bi ts 0 to F ADRO to ADRF are used to address up to 64K bytes of memory Parallel I O port C bits 0 to 3 can be used as additional address lines to expand memory addressing Address line ADF is jumperable to either the CPU address output or one of the port C bits Figure...

Page 31: ...H r ODD f 00 7 0 7 00 7 EVEN EVENIWORD BYTE 8000H 08 15 C l 08 15 EVEN Z8002 Figure 3 1 196 4116A to Multibus Interface OFFBD BUFF EN 8 ADR12 2 ADR11 38 ADR10 MULTIBUS 0 P1 36 63 0 0 ADF 0ADO to ADE 12 68 P 1 o 10 65 peo 0 0 1 1458 PC2 0 0 1 16 59 PC3 O I From CPU 0 _ Figure 3 2 Memory Expansion 3 3 ...

Page 32: ... serial interface at P5 The modified serial I O port does not use the Data Set Ready and Clear To Send lines Programmable operating modes and format options allow the Am9551 to service a wide range of communications disciplines and applications Operating modes are determined by a mode instruction word and a command instruction word Am9551 INITIALIZATION The Am9551 chip is initialized as follows Re...

Page 33: ...r synchronization Single or double character Sync For asynchronous mode Baud rate multiplier Character I ength Parity enable disable Even odd pari ty Number of stop bits The mode instruction word formats for synchronous and asynchronous modes are shown in figures 3 3 and 3 4 respectively Am9551 SYNC CHARACTERS In the synchronous mode one or two sync characters must be written to the command regi s...

Page 34: ...de 64 x Baud rate factor 00 5 bits per character 01 6 bits per character 10 7 bits per character 11 8 bits per character o Parity disable 1 Parity enable o Odd parity 1 Even parity 00 Invalid 01 1 stop bit 10 1 stop bits 11 2 stop bits Figure 3 4 Am9551 Asynchronous Mode Control Code Am9551 STATUS READ The CPU can determine the status of the Am9551 any time by issuing an I O input to addresses FFD...

Page 35: ...icates the asynchronous mode byte stored in the recei ver character buffer was recei ved with incorrect character bit format When Sync Detect is set for internal sync detect this bit indicates character sync has been acheived and the Am9551 is ready for data Data Set Ready is set by the externa1 Data Set Ready Signal to indicate the communications data set is ready 7 6 5 4 3 2 o It Bit No TxEN 1 E...

Page 36: ...d port on each chip is used as control lines for ports A and B in some modes The operating modes of the ports are controlled by outputting either an operation control word or a bit set reset control word Table 3 2 is a configuration guide for the Am8255A Am8255A ADDRESSING There are four consecuti ve word addresses FFE8H through FFEEH for contro1 data transfer and status read See table 3 1 for the...

Page 37: ...ctions Bit 0 Cannot be used Bit 1 and 2 Can be used as input or output if port B is in mode O Bit 3 INTR Interrupt Request output for port Bit 4 STR Strobe input for port A Bit 5 IBF Input Buffer Full output for port A Bit 6 ACK Acknowledge input for port A Data flow direction control for 8304 via jumper 105 111 Bit 7 OBF Output Buffer Full output for port A EFFECT Enable input at U3 Enable input ...

Page 38: ...Performs the following dedicated functions Bit 0 INTR Interrupt Request output for port B Bit 1 IBF Input Buffer Full output for port E5H Bit 2 STB Strobe input for port B Bit 3 Can be used as input or output if port A is in mode O Bits 4 to 7 Can be used as input or output if port A is in mode 0 or in some combinations where port A is in mode 1 These bits are always dedicated when port is in mode...

Page 39: ...hown in figure 3 7 Am8255A BIT SET RESET CONTROL WORD LJhen operati ngi n mode 1 or 2 thE bits of the port C can be set or reset using the bit set reset control word The functions of some port C bi ts are defi ned by port A and B operations in modes 1 and 2 Refer to table 3 2 for porot C bit definitions in modes 1 and 2 Figure 3 8 shows the bit set reset control word format L Port C an 0 3 1 Input...

Page 40: ...r later servic NOTE When using Multibus interrupts the 8259A must be used in the edge trigger mode INITIALIZATION The 8259A accepts two types of command words Initial ization Command Words ICWs and Operation Command Words OCWs Before normal operation can occur the 8259A must be initialized Initialization consists of three ICWs ICWl ICW2 and ICW4 The ICWs are shown in figure 3 9 The ICWI format for...

Page 41: ... 6 1 1 1 7 01 DO I AEOI I 1 I Must be 1 For 16 Bit lAP 1 Automatic End of Interrupt 0 Normal EOI 1 Special Fully Nested Mode o Normal Nested Mode O Not used by Am961 4116 03 Must 0 Vector Address Bits includes A8 A10 which are inserted by 8259A for low order address 8 bits L A1 07 06 05 D4 03 X L TI M r F A1 07 06 05 D4 03 r 0 o D F N M O O 00 D4 00 I 1 G A14 A12 LA I O OCR FFC8H ICW1 ICW2 I O OCR...

Page 42: ...es the three DeWs OCW1 is the interrupt mask register When a particular bit is set the corresponding interrupt input is masked inhibited Any bits cleared will enable the corresponding interrupts Reading the IRR allows the programmer to look at which bits are masked or unmasked Bit 0 of DCW1 is input 0 and bit 7 represents input 7 The OCW2 format uses bits 5 through 7 for control of the Rotate and ...

Page 43: ...ically Mode A 1 EO to E7H Rotate at EOI Mode B LO L2 Code of Line I 0 BOH Set Rotate A FIF LO L2 0 0 I 0 OOH Clear Rotate A FIF LO L2 0 0 COH Rotate Priority Mode B Independent of EOI OCW3 I O AOOR FFG8H 02 01 DO P I ERIS I RIS I Don t Care o o o 1 No Action o Read IR Reg on Next RD Pulse Read IS Reg on Next RD Pulse o o o No Action Polling Mode o Interrupt Mode o Reset Special Mask 1 Set Special ...

Page 44: ...ts set in OCW1 even if an EO I command was not received to reset the corresponding ISR bit Bit 2 of OCW3 selects either the polling mode bit 2 1 or interrupt mode bi t 2 0 When the poll i ng mode is acti ve a CPU read at address FFC8H is treated as an interrupt acknowl edge The corresponding ISR bit is set to indicate which interrupt input needs service The byte read at FFC8H contains two pieces o...

Page 45: ...a Pointer Co Counter Mode Re Counter Load Re General Counter LEMENT BIT SIZE QUANTITY Bit 1 5 unter 4 1 unter 5 1 6 1 r 8 1 ng Counter 16 1 istcr 16 1 16 2 16 2 gister 16 5 gi ster 16 5 gister 16 5 16 5 Counter Hold Re Alarm Register Comparator Status Register Output Control FOUT Divider Co TABLE 3 3 CONTROL ELEMENT SUM 1ARY CONTROL E Command Reg j ste Frequency Seal i Master Mode Reg COMMAND REGI...

Page 46: ...commands is important Allows counter specific service routine to control individual counters regardless of the operating context of other counters STATUS REGISTER The 8 bit read only status regi ster i ndi cates the state of the Byte Poi nter bit in the Data Poi nter regi ster and the state of the OUT signal for each of the general counters shown in figure 3 12 The OUT signals reported are those i...

Page 47: ...f t _ _ _ t j 1it ___ i _ S_1 _ ii t tEi ij i f _ 1 1 1 0 i 1 0 to _ _ _ 1 1 I 1 0 1 1 1 t 1 1 i 1 0 1 1 1 1 Set 1 0 O O 1 0 _ I l 1 1 6 t t i o n 6 t I 1 Q 1 Mas _ _ _ MASTER MODE RI GISTER The 16 bit Master Mode MM register is used to control those internal activities that are not controlled by the individual Counter Mode registers This includes frequency control time of day operation comparator...

Page 48: ...nabled 6 Input 11 TOO Enabled 10 Input Figure 3 13 Master Mode Register Bits TIME OF DAY Bits MMO and MM1 of the Master Mode register specify the time of day TOO options When MMO a and MM1 0 the special logic used to implement TOO is disabled and counters 1 and 2 will operate in exactly the same ways as counters 3 4 and 5 When MMO 1 or MM1 1 additional counter decoding and control logic is enabled...

Page 49: ... COMPARATOR ENABLE Bits MM2 and MM3 control the Comparators associated with Counters 1 and 2 When a Comparator is enabled its output is substituted for the normal counter output on the assoc jated OUT1 or OUT2 pi n Once the compare output is true it remains true until the count changes and the compari son therefore goes false The two Comparators can a1ways be used individually in any operating mod...

Page 50: ... is off and ina 1ow impedance state to ground MM12 can be set or cleared in conjunction with the loading of the other bits in the Master Mode register alternatively there are commands that allow MM12 to be individually set or cleared directly without changing any other Master Mode bits After power up or reset FOUT is gated on BUS WIDTH Bit MM13 controls the multiplexer at the data bus interface in...

Page 51: ... the general counters and to the FOUT divider The scaler is tapped every four bits and can be programmed to divide in binary or in BCD The combinations of frequencies thus available are shown in figure 3 15 For example if the base oscillator frequency is 8fVlHz the F4 frequency will be 8KHz when BCD seal i ng is sel ected If the base osci 11 ator frequency is 8MHz the F3 frequency wi 11 be 31 25KH...

Page 52: ...ta port The Data Pointer is directly loaded by command and can be automatically incremented following data transfers Figure 3 16 shows the pointer configuration The Byte Pointer bit is only active when the data bus is operating with its 8 bit width option Whenever the Data Pointer is loaded the Byte Pointer bit cleared to zero The Byte Pointer toggles following each 8 bit data transfer with an 8 b...

Page 53: ... E1 1 and E2 1 only the Group field is sequenced This allows the Hold registers to be sequentially accessed while bypassing the Mode and Load registers Once the Am9513 is operating the two illegal codes shown in figure 3 16 for the Group Pointer field will not occur because no commands wi 11 load the ill ega1 va1ues into the Group Poi nter and no automatic sequencing will change the Group Pointer ...

Page 54: ...d before attempti ng to read the saved data A Data Port wri te to another register will also initiate a prefetch subsequent reads will access the recently saved Hol d regi ster data Many systems wi 11 use the sa vi ng gate edge to interrupt the host CPU In systems such as this the interrupt service routine should issue a Load Data Pointer command prior to reading the saved data COUNTER LOGIC GROUP...

Page 55: ... or by software commands at any time COUNTER MODE F EGISTER Each Counter Logic Group includes a Counter Mode CM register used to control all of the individual options available with its associated general counter These options include output configuration count control count source and gating control Figure 3 17 shows the bit assignments for the Counter Mode rE gisters The following paragraphs des...

Page 56: ...E N 101 Active Low Level GATE N 110 Active High Edge GATE N 111 Active Low Edge GATE N Count Source Selection OXXXX Count on Rising Edge 1XXX X Count on Falling Edge XOOOO TCN 1 X0001 SRC 1 X0010 SRC 2 XOOll SRC 3 X0100 SRC 4 X010l SRC 5 X0110 GATE XOlll GATE 2 Xl000 GATE 3 Xl00l GATE 4 Xl0l0 GATE 5 Xl0ll Fl Xll00 F2 Xll0l F3 Xlll0 F4 Xllll F5 _ L _ __ l _ L _ _ J L _ L _ JL _ _ _L_ __ _JL_ _ L__ ...

Page 57: ...l indicate the counter state that would have been zero had no parallel transfer occurred COUNT CONTROL Counter Mode bits CM3 through CM7 specify the various options available for direct control of the counting process Most of the control bits operate rel ati vely ii ndependently of the others so that they can be combined freely to fonn many types of counting configurations Bit CM3 speci fi es i nc...

Page 58: ...allow retriggering and the selection of Load or Hold sources for counter reloading The use and definition of CM7 depends on the status of the Gating Control field and bits CM5 and CM6 hen some form of Gating is specified CM7 control s hardware retriggering In this case when CM7 0 hardware retriggering does not occur when CM7 1 the counter is reloaded any time an acti ve Gate input occurs Any timE ...

Page 59: ...n 36 can be used to perform the gating function This also allows a single Gate pin to simultaneously control up to three counters For codes of 110 or 111 in this field counting proceeds after the specified active Gate edge until one or two TC events occur Jithin thi s interval the Gate input is ignored except for the retri ggeri ng option When repet ition is selected a cycle is repeated as soon as...

Page 60: ... More details of the toggle activity are included in the Counter Mode Register description BAUD RATE PROGRAMMING The Am96 4116A uses the Am9513 System Timing Controller as the on board clock source for the two serial ports As shipped both ports are set to function at 9600 baud FOUT from the Am9513 The Am9551 clock sources may jumpered to Am9513 OUT3 U6 and OUT4 U22 OUT3 and OUT4 are the outputs of...

Page 61: ...stem output for selecting Normal user or System pri vi 1eged memory space a Byte Word output to permit addressing of either bytes B bit or 16 bit words Decoding of the status outputs is provided for I O functions code or data functions and memory operations One decoded signal is I FETCH which can be jumpered and used externally to select either code or data areas of off board mE mory The Normal Sy...

Page 62: ...0 SERIAL 110 SERIAL 1 0 CLOCK I 16 16 f II l 1 II 1 1 8 16 BIT I ADORESS AOORESS AOORESS RESET BUFFER BUFFER CIRCUITS I I I L J MULTI AmZlIOO2 MASTER CONTROL 16 t 16 BIT DATA DATA DATA BUFFER 1 6 16 6 18 BUFFER RAM 32K ROM Am9513 8259A BYTES 214 8 KBYTES SYSTEM TIllING INTERRUPT DUAL ACCESS CONTROLLER CONTROLLER fa I I INTERRUPT JUMPER PINS P2 P1 Figure 4 1 Am96 4116A MonoBoard Computer Block Diag...

Page 63: ...ic consists of digital comparator U85 Jumpers are ava i1ab1e to determi ne the address an external processor uses to access the Am96 4116 RA 1 The output of U85 dri ves a synchronizing flip flop U81 to produce ZBUSRQ to request the bus from the AmZ8002 The CPU will respond with ZBUSAK Bus transceivers U87 U8B and U95 provide data bus buffering between the AmZ8002 and the off board d vi ces and mem...

Page 64: ... DB OF ODD 0 US7 dd Byte Data Transfer en Byte Data Transfer Word Data Transfer EJ r I B J 0 08 DF EVEN CPU r I DO D7 1 ODD A OS OF f EVEN CPU DO D7 ODD B a D8 DF EVEN CPU r I I DO D7 f 1 ODD C E Fi gure 4 2 CPU Memory Operat ons 4 4 ...

Page 65: ...3 provides synchronization of refresh and memory availability with both a dE layed CPU clock and the 77 KHz refresh clock ROM EPROM The on board ROM consists of two devices of lK 2K or 4K byte capacity each for a maxi mum of 4K words or 8K bytes One ROM U91 is for odd byte addresses bi ts 0 to 7 and U75 is for even byte addresses bits 8 to F Jumpers are provided for selection of ROM type Both ROMs...

Page 66: ...ficant bit The 1 rn9551 will subsequently transmit serial data to an external device if the transmitter is enabled An input instruction Serial 2 CE 10 REAO and C O high causes the Am9551 to place a status byte on the data bus The status bits are the resul t of status and error checki ng funct ions performed wi thi n the Am9551 An input instruction al so causes the Am9551 to output a data byte onto...

Page 67: ...i ved SYNDET is reset when the status buffer is read or llhen a reset soj gna1 is acti vated SYNDET wi 11 perform as an input when the external synchroni zation mode is programmed External logic can supply a positive going signal to indicate to the Am9551 that synchronization has been achieved This will cause it to initiate the assembly of characters on the next falling edge of RxC To successfully...

Page 68: ...transmit data if the TxEN bit in the command byte is a one CTS is generally used as a response to RTS by a modem to indicate that transmission can begin Designers not using CTS in their systems should remember to tie it low so that n9551 data transmission will not be disabled PARALLEL I O INTERFACE The Parallel I O Interface on the Am96 4116A provides 24 lines for the transfer and control of data ...

Page 69: ...Interrupt Controller and a jumper pad that allows the user to connect any of 32 possible interrupt requests to the 8259A eight interrupt priority inputs The Interrupt Controller resolves priorities among the eight levels The priority resolution algorithm can be changed dynamically at any time This means that the complete interrupt structure can be modified as required The operation of the Interrup...

Page 70: ...on of the four control lines CS TIMER CE enables the Am9513 whenever timer CPU operations take place C O ASl is address bit 1 When AB1 is high the control and status registers are available to the CPU When AB1 is low data regi sters are accessible to the CPU RD 10 READ permi ts readi ng of status regi sters or data from the Arn9513 dependi ng on the state of AS1 WR 10 WRITE permits writing of cont...

Page 71: ...rovide you with fast efficient service When reshipment is due to the product being damaged duri ng shi pment fy omAMC or when the product is out of warranty a purchase order is requ i red for the AMC Fi el d Servi ce Department to initiate the repair Prepare the product for shi pment by repackagi ng it in the ori gi na1 factory packagi ng mater j a1 if ava i 1ab1e When the ori gi na1 packagi ng is...

Page 72: ...U1 I N Figure 5 1 Am96 4116A MonoBoard Computer Component Locations o I no I yo I o I 1 I ...

Page 73: ...85 6 P4 13 C47 22 F Tl o l _ _I t12 1 PI 3 4 5 81 92 83 84 r I 1 B c 111 I w A NOTES UNLESS OTIiERV 15E SPECIFIED ALL RESISTORS AUJES ARE IN O S 1 4 w 5 ALL CA A iTOR VALUES t R J i i FA A j i L EvEN NUMD RED PIN 1 1 F3 ORE CGiJ J C1EC TO OI i D L _ _ Figure 5 2 Am96 4116A MonoBoard Computer Schematic Diagram ...

Page 74: ...D B 1 pt OFF oD uFEN SeE SHT 1 D c B A _ _ Figure 5 3 Am96 4116A MonoBoard Computer Schematic Diagram ...

Page 75: ... J1 I J1 o 1 c I B A 7 S CE 5 _ _ f 0 E 4 2D 5 E 3 D5OURCE2 SOURCE I o B A Figure 5 4 Am96 4116A HonoBoard Computer Schematic Diagram ...

Page 76: ... ON 1 _ _ _ TE G 5 RPS T P t 7 _ _ _ _ _ 3 T2 1 5 TI Ei Ea 2 1l A Micro r 1 r 7 t i s r r E iJ D A C R c A M i 25 ONO BOA D t t L l ___ _ _ _ _ _ _ _ _ a_ _ i DO TSO W i JTI1 J222 5s I I r l AJl5 _ _ A Z l A I 5 11 RAI via __i jf ___i r_ J PJ RAS __i t 1I t __i t 5 1 C 5H f I I I AI 77 H2 _ _ D B c A l Figure 5 5 Am96 4116A MonoBoard Computer Schematic Diagram ...

Page 77: ... iO 19 E EN 8Y1E I I 8K TE C E 0 7o _ __ l I p c lulO t S 44 eASL O C5 I L _ _ __ r I _ _ _ _ _ _ _ __ _ _ 1 RAM wE 4 o _ _ f J _ _ rl _ _ _ _ _ _ _ __ c 3 O i1 _ __ S T 5S z 3 p ____ _ _0 __ _ _ _ S i T 51 3 a _I B c D Jl I I A _ __ _ Figure 5 6 Am96 4116A MonoBoard Computer Schematic Diagram ...

Page 78: ...S T H HIIM T CE H _ 8 f Q H __ _ _ _ I Cl TI E OUT _ c D J1 I 00 OII UF l _ i r _ u 4 o 9 NH1 P8 i 240 u j B A 11 1 12 1Iol D S _ 3 I VIACK_ f lT 414 r q I Z ll C gt J L t f U A I _i 5 O 1 ll a I L J _ t J r r __ _ _ _ _ OO E 7 t I _ _ _ _ 1 9 Ad onoed Mioo Corr pulen i SCHEMAT DiXiRAM K Pn MOi JI BOARD Nll l 7 _ _ __ Figure 5 7 Am96 4116A MonoBoard Computer Schematic Diagram ...

Page 79: ...r fl S2 4 PC 5 IIl H c Am96 4116A MonoBoard Computer Figure 5 8 4 81 _ fli77 l Pl Ill it ttlr S i t HI t 11 0 f D6 7 2 2 D DIl2 Dill lDll_ t 1I1 Z tll A 2 a I 53 2 DI 4 20 4 1 1 A85 2 AB9 AliA DSF aE P P D 2 1l DIU 011 rl Na ClOlI 6YTE I HI a 01 r 4 1i t t IFF 50 IOFEH 1l9 3 Cl VIE I r HI euSEH 10 01 IIU _ _ _ _ Il Pl R _ _ 5 11 IloI6 2 I _ IS o4U BI til 5 _ J e f7 _ r t _t _ i 1 _J J2_ _ 0 _ __ _...

Page 80: ...A D B c l I l pC7 f P 3 n PC f L PC 5 1 C PC S l i 1 1 D 8 c A In I o Figure 5 9 Am96 4116A MonoBoard Computer Schematic Diagram ...

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Page 85: ...Department 3340 Scott Boulevard Santa Clara CA 95051 _ __1 TITLE Am96 4116A AmZ8000 16 Bit MonoBoard Computer PUBLICATION NO 059910090 001 Revision A COMMENTS Dl3scribe errors suggeste d additions or deletions and include page numbers etc From Name Company Address Position ...

Page 86: ...Advanced Micro Computers A subsidiary of Advanced Micro Devices 3340 Scott Boulevard Santa Clara California 95051 408 988 7777 TELEX 171 142 ...