Advanced Micro Computers AmZ8000, User Manual

Page 1: ...Advanced Micro Computers Distributed by Advanced Micro Devices Am96 4016 AmZ8000 Evaluatiion Board User s Manual ...

Page 2: ... tA tfflyr DN L t9J4P 1V i21 JMv V 1 I 1 I _ 1 1 1 Publication No 00680131 Address comments concerning this manual to REVISION LEITERS I 0 0 AND ARE NOT USED Copyright 1979 Advanced Micro Computers Printed in U S A ii ADVANCED MICRO COMPUTERS Publications Department 3340 Scott Boulevard Santa Clara CA 95051 ...

Page 3: ...ccurate and compl ete at the time it was pri nted However AMC reserves the right to change specifica tions without notice No responsibility is assumed for errors that might appear in this manual No part of this manual may be copied or reproduced in any form without prior written permission from AMC Publications related to this manual include AmZ8002 CPU Data Sheet AmZ8000 Family Interface Manual A...

Page 4: ......

Page 5: ...5 D x y Display Mlemory 3 5 E x Hardware Breakpoint u 3 5 F x y z Fill Memory 3 5 G x Execute Program 3 6 H n Set Half Carry Flag 3 6 LOAD d file x Down Load 3 6 M x y z Move Memory 3 6 NM Enter Normal Mode 3 6 P n Set Parity Flag 3 6 P x Fill Program Counter 3 6 RHn x Fill High Byte Register 3 6 RLn x Fill Low Byte Register 3 6 Rn x Fill Word Register 3 6 SAVE d file x Y Up Load 3 6 SM Enter Syst...

Page 6: ......

Page 7: ...2 3 2 2 Driver Terminators for Parallel Ports 2 3 2 3 Other Driver Terminator Circuits for P3 2 3 2 4 PI Connector Pins 2 5 2 5 P2 Connector Pins 2 6 2 6 P3 Connector Pins 2 11 2 7 P4 Connector Pins 2 12 2 8 P5 Connector Pins 2 12 2 9 P6 Connector Pins 2 13 3 1 Monitor Command Summary 3 4 3 2 Monitor I O Control Block 3 9 4 1 Peri pheral Addresses 4 6 4 7 5 1 Am8255A Operation Control Word Format ...

Page 8: ......

Page 9: ...er in ROM Keyboard Display console CRT termi nal Universal prototyping board CPU bus backplane 2 or 3 slots Six board card cage 64 kilobyte memory expansion Compl ete AmSYS 8 8 Development Sys tern with di skette storage i nter face utilities and PASCAL like mac roassembler for the ArnZ8000 series Programs can be entered and executed in either the stand alone or Development System confi gurat ion ...

Page 10: ...EL I O P3 KEYBOARD DISPLAY I I P4 P5 P6 50 pin IAm 8255A r Driver Terminator Sockets 8 Kilobytes Am 9050C RAM M4716 EPROM itor and Assembler 86 pin P1 POWER AND GROUND Break Switch N 8 00 N E 60 pin P2 CPU BUS 1 2 Figure 1 1 Board Layout ...

Page 11: ...n the AmSYS 8 8 is attached for up down loading of programs the Develop ment SystemIS console can communi cate with the Eval uation Board to control all functions The Development System contains a com prehensive set of hardware and software resources to fully utilize AmZ8000 cap abi 1it ies The system i ncl udes dua1 diskette drives 64K bytes of RAM se rial and parallel ports and a multi master bu...

Page 12: ... baud rate control third counter available to user 12VDC 085A 12VDC 06A 5VDC 1 65A without optional keyboard display console or 5VDC 2 0A with optional keyboard display console 12 011 305 rrrn x 6 75 11 172 rnm MULTIBUS form factor with six edge connectors PI through P6 Memory Addressi ng ROM space RAM space 0 2FFF H 4000 5FFF H 1 4 Environmental Conditions Edge of Card Connectors Monitor o to 55 ...

Page 13: ...d Display 56 key keyboard with 20 character alphanumeric LED display Same physical form as Am96 4016 Evaluation Board with attaching standoff con nectors and interconnection ribbon cable P6 P5 P4 r 1 r I I I Keyboard RS232C RS232C Interface Interface or 20mA Interface I I 8253 9551 9551 I Counter Serial Serial Timer I O I O j j j 2 1 j 1 4716 9050C EPROM RAM I 12V 12V HiV L_ J P1 P3 Ie Jrivers Ter...

Page 14: ...play P3 Am SYS 8 8 Development System Flat cable to Development System CPU board for control and up down loading P1 P2 i Power and Ground CPU bus backplane board 2 or 3 slots for interconnecting external prototyping or memory expansion boards Figure 1 3 Standard Configurations 1 6 ...

Page 15: ...t I O port addresses allowing up to 64K ports although in the Evaluation board implementation the upper four address bits are not decoded and often the lower one or two address bits are used for sub addressing within peripheral circuits The Evaluation Board also implements onl y 8 bi t I O transfers on the four top edge connectors P3 through P6 These are the lower 8 bits on the data bus The 24 par...

Page 16: ...l e on the AmSYS 8 8 The full CPU instruction set can be used to create very powerful appl ica tion programs The 110 basic instruc tions have permutations around operand addressing modes plus autoincrement and autodecrement facilities Code written for the ArnZ8002 is source compatible with the AmZ8001 micro processor Most instructions are between one and three 16 bit words in length Instruc tions ...

Page 17: ...quire setup before the board can be used These are the six edge connectors PI through P6 pl us sockets for ROM or E PROM and the sockets for parallel I O driver or terminator circuits Each of these groups is discussed individually below NOTE When one of the standard config urations illustrated in Figure 1 3 has been ordered from AMC only the following installation connections need be considered Ed...

Page 18: ...ETS FOR Am 8255A PARALLEL I O U2 U7 Keyboard Parallel Display Serial Serial I O Console I O I O P3 P4 P5 P6 50 pin 86 pin P1 Power and Ground ROM EPROM U57 U62 60 pin P2 CPU Bus 2 2 Figure 2 1 Edge Connectors and IC Sockets ...

Page 19: ...OR PARALLEL PORT Device 74LS3j 74LS37 74LS3j iSBC902 iSBC902 i SBC902 Function Socket Dr j ver U2 Dr j ver U3 Dr j ver U4 Tenni nator U5 Tenni nator U6 Tenni nator U7 TABLE 2 3 OTHER DRIVER TERMINATOR CIRCUITS FOR P3 Drivers Terminators 7438 74LS38 7437 7 LS37 7432 7i LS32 7426 7i LS26 7409 7i LS09 7408 7i LS08 7403 71 LS03 7400 71 LSOO Intel Intel Nat ional National National iSBC 901 iSBC 902 BLC...

Page 20: ...an be used for external initializing re set when jumpered for thi s function see figure 2 4 The pi n connections are shown in table 2 4 2 4 P2 a 60 pin connector physically compatible with the Mu1tibus and i5BC 80 formats It car ries buffered signals from all CPU lines except 5V which is on the PI connector and DE COUPLE wh ich is not used on the AmZ8002 The address data bus from the CPU is demu1 ...

Page 21: ...NS Component Side Solder Side 1 GND 2 GND 3 5V 4 5V 5 5V 6 5V 7 12V 8 12V 9 N C 10 N C 11 GND 12 GND 13 N C 14 INIT 15 N C 16 N C 73 N C 74 N C 75 GND 76 GND 77 N C 78 N C 79 12V 80 12V 81 5V 82 5V 83 5V 84 5V 85 GND 86 GND 2 5 ...

Page 22: ...REQ 13 N S 14 B W 15 BUSRQ 16 BUSAK 17 MI 18 MO 19 RST 20 WAIT 21 PHI clock 22 STOP 23 NMI 24 N C 25 STO 26 ST1 27 ST2 28 ST3 29 AO 30 Al 31 A2 32 A3 33 A4 34 A5 35 A6 36 A7 37 A8 38 A9 39 A10 40 All 41 A12 42 A13 43 A14 44 A15 45 DO 46 01 47 02 48 03 49 04 50 05 51 06 52 07 53 08 54 09 55 010 56 011 57 012 58 013 59 014 60 015 ...

Page 23: ..._ r _ 1 I I I I I I I I _ P2 1 I I L_ I I B A 7 P1 BACKPLANE f It I Am SYS 8 8 96 4016 I 96 6410 96 1064 CPU Evaluation I Prototype RAM Board P4 P3 Board I Board Board I j __ J j j _ It r I L It Am SYS 8 8 Am SYS 8 l Disk RAM Controller Board Board P2 BACKPLANE Fi lure 2 2 Connecting to the AmSVS 8 8 2 7 ...

Page 24: ...Keyboard Display A 26 2 26 2 P4 Evaluation Board COMPONENT SIDES UP 2 8 B Figure 2 3 Connecting the Keyboard Display Console ...

Page 25: ...L _ _ J Figure 2 4 Jumper Option 2 9 ...

Page 26: ... vice 2 10 The I O port address for data through this connector is FEF or FED they are equivalent The pin connections are given in table 2 8 Parenthesized numbers are the correspondi ng EIA pin numbers for RS232C See the Am9551 and Am8253 Data Sheets for more details P6 26 pin connector to the RS232C or 20mA current loop TTY interface of one of the two Am9551 serial I O circuits The RS232C interfa...

Page 27: ...PB3 10 GND 11 PB 12 GND 13 PBI 14 GND 15 PBO 16 GND _ 17 PC 3 Port FF2 18 GND 19 PC 20 GND 21 PCI 22 GND 23 PCO 24 GND 25 PC4 26 GND 27 PC 28 GND 29 PC6 30 GND 31 PC7 32 GND _ 33 PA7 Port FFO 34 GND 35 PA6 36 GND 37 PAl 38 GND 39 PA4 40 GND 41 PA3 42 GND 43 PA 44 GND 45 PAl 46 GND 47 PAD 48 GND _ 49 N C 50 GND 2 11 ...

Page 28: ...I 20 ID2 21 ID3 22 ID4 23 ID5 24 ID6 25 GND 26 5V TABLE 2 8 P5 CONNECTOR PINS Solder Side RS232 Component Side RS232 1 CHASSIS GND 2 N C 3 TRANSMITTED DATA 2 4 N C 5 RECEIVED DATA 3 6 N C 7 REQUEST TO SEND 4 8 N C 9 CLEAR TO SEND 5 10 N C 11 DATA SET READY 6 12 N C 13 SIGNAL GND 7 14 DATA TERM RDY 20 15 N C 16 N C 17 N C 18 N C 19 N C 20 N C 21 N C 22 N C 23 CLKO 24 GATEO 25 OUTO 26 SIGNAL GND ...

Page 29: ... TO SEND 11 DATA SET READY 13 SIGNAL GND 15 DATA CARRIER R 17 N C 19 N C 21 N C 23 TTY RX 25 TTY TX RS232 Component Side RS232 I 2 N C TA 2 4 N C 3 6 TTY RDR CONTROL 16 D 4 8 N C 5 10 N C 6 12 N C 7 14 DATA TERM ROY 20 TN 8 16 TTY RDR CONTROL RTN 21 18 N C 20 N C 22 TTY RX TRN 24 12 L 4 TTY TX RN 25 13 6 SIGNAL GND 2 13 ...

Page 30: ...ection entitled Principles of Operations 2 14 Expansi on memory can be of any type compatible with the available pins and the buffered electrical characteristics at P2 see appendix A Dynamic memory refresh may be done on the external board or it may use the CPU refresh cy cle as does the on board RAM The 64K RAM board supp1 ied by AMC is compatible with both the Evaluation Board through P2 and wit...

Page 31: ...d 13 If the NMI line on P2 is to be used the Break sW j tch must be disabled by cutting the trace con necting jumpers 12 and 13 The wire wrap pins at 12 and 13 can be used to reconnect the Break switch at a later time Jumper 1 2 Whenjumpered it connects the chassi s ground of the external serial I O device at P5 to the Evaluation Board ground Jumper 3 4 When jumpered it connects the chassis ground...

Page 32: ...00 5FFF is addressed thereby disabling off board memory When jumpered 17 to 18 the INH ltne becomes an input for all memory ac cesses thereb Y disabling on board memory when the line is low 2 16 Jumper 19 20 When j umpered it di s ables the Wait cycle normally in serted between the T2 and T3 cycles of on board memory cycles tt 2 J FIH 1 f ...

Page 33: ...the Monitor includes hex addresses 0 through 5FFF as i ndi cated in fi gure 3 1 Both the Monitor and the optional Assemb1 er a1 so use up to 100 hex bytes each of RAM starting with address 4000 for the system stack and working stor age at various times If the P3 P4 and P6 edge connectors are used for non standard I O i e any way other than that illustrated in fi gure 1 3 or if the P5 connector is ...

Page 34: ...ge for Monitor 4000 thru 40FF r ROM L r i FFFF I I I I I I I I J Optional j l Off Board r I Memory I I I I I I I I I I I 1 1 6000 RAM 3000 Assembler Optional 1 1 1000 j Monitor 0 T ON BOARD MEMORY 3 2 Figure 3 1 Memory Address ...

Page 35: ...BOUT key on Teletype TTY consoles Also the entire cur rent line of entry can be deleted with the Control X key pair If unrecogni zed commands are entered the Monitor wi 11 respond wi th a ques tion mark 3 3 MONITOR COMMANDS The Monitor commands are listed accord i ng to funct iona1 categori es in tab1e 3 1 Upper case characters are literal entries lower case characters are variable entries The com...

Page 36: ...g Set decimal adjust flag Set half carry flag Set overflow flag Set parity fl ag Set sign flag Set Zero fl ag Execution Functions Execute assembler Execute program Enter system mode Enter normal mode Hardware breakpoint Software breakpoint Single step Trace Up Down Loading Down Load Up Load NOTE m n are decimal values x y Z are hexidecimal values D x y S x XP X Xn XF F x y z P x RHn x RLn x Rn x M...

Page 37: ...y command See the XF command for displaying flags 3 9 0 x y DISPLAY MEMORY Displays the contents of memory at ad dresses x through y Up to eight hexi decimal words p1 us thei r ASCI I byte equivalents and beginning address are displayed on each line Bytes with no ASCII equivalent are represented by an underline this character may vary with your terminal The y ending address is optional and if miss...

Page 38: ...t hex val ue x the AmSYS 8 8 format with the disk The register can be displayed with the drive specified The HOST program must l xn command be Y unni ng on the Development System J I r ff f f 7 J If this command i t ered f O the De 3 20 RLn x FILL LOW BYTE velopment System a prompt cons i sti ng REGISTER of the currently logged in diskette Fills the low byte register n where n identifier in parent...

Page 39: ...return onl y w ill advance to the next word without substitution A peri od wi 11 termi nate substitut ion and return to the Monitor s command mode Substi tut ions of addresses 0 or 1 can conflict with the Sn command To avoid this conflict these addresses may be represented by IJ and respec tively 3 26 T m n TRACE Executes m instructions beginning at the current program counter address and displays...

Page 40: ... number of bytes to be wri tten on read as descri bed in the following function code description Read Control Statement function code 0 Thi s command is intended for use by the assembl ere It transfers the user call command line to the specified area in the same form as the Read Console function code 1 Read Console function code 1 Reads a single line from the console The fi 1e name address is unus...

Page 41: ...nt No entry Response code is stored here after I O Address at which the file name is stored Beginning address of data to be written or read Data written must include any necessary carriage return line feeds etc Data read wi 11 inc1ude t hem a1so Length in number of bytes It indicates either the total number of bytes to be writ ten or the maximum number of bytes to be read The total number of bytes...

Page 42: ...SYS 8 8 Store programs by uploading the memory image from the Evaluation Board to a file on AmSYS 8 8 The file is uploaded with the SAVE Moni tor command and can later be downloaded again with the LOAD Monitor command The section should be called _ ROST AND MONITOR C D k F 1 f t d COMMUNICATION reate 1 S 1 e unc lon co Create a disk file and prepare The capabilities should be listed in a more reas...

Page 43: ...n Board programs must start no lower than about 4100 hex see figure 3 1 Invalid Control L COMMAND ERROR command zaooo MESSAGE PENDING A prior mes sage to the Evaluation Board CPU has not yet been acted upon ILLEGAL REQUEST FROM zaooo The Development System has received an un recogni zed message from the Eval ua tion Board After an up or down load the HOST pro gram can be terminated with the Contro...

Page 44: ... Tlhi s fi 1e can then be down loaded to the Evaluation Board by first running HOST and then enteri ng the Eva1uat ion Board Monitor s LOADc ommand The section shojThe section lshould be called SAVE RESTORE with UPLOAD DOWNLOAD The AMe binary i information asThe user can save the memory image of an AmZ8000 COM file the program by uploading to AmSYS 8 8 The SAVE Monitor code Like a command saves th...

Page 45: ...tem Normal flag set to Sys tem Mode The Monitor program then be gins execution The Monitor writes a value to the CPU s refresh counter that causes refresh at 30 microsecond intervals The program status area poi nter i nterrupt vector table is also written Then the Mon itor writes control bytes to the Am8253 counter timer the two Am955l serial I O ci rcui ts and the Am8255A parall el I O circuit It...

Page 46: ...T2 and T3 clock cycl es of a memory cycl e duri ng memory references to address 0 5FFF STOP input Not used It stops the CPU entirely which prevents the Monitor pro gram from executing BUSRQ input Not used on board since only the CPU controls the system buses 4 2 MO output Not used RESET i nput Connected to the RST line on the board which resets the CPU and all other programmable cir cuits during p...

Page 47: ... 1 X X 1 1 x 1 X 1 1 Figure 4 1 IOR and IOW Decoding Breakpoint Comparator _I _O__ 8 _ I_ _M_e_m_o_r_ y _ 1 1 09 I o 0 roO c L Q VI E NMI L a t C h CPU T r a n s C e i v e r I Address Bus INH L scl e_iv_e_r Data Bus DO D15 P2 Figure 4 2 Bus Structure 4 3 ...

Page 48: ...memory are enabled irrespective of whether the operation is on a byte or a word In a byte write to RAM however only 4 4 the high or low byte of memory is enab1ed i nterna1 data bus 1i nes IOl5 108 or 1 7 1 0 respectively By contrast all ROM transfers enabl e the entire word A single Wait state is inserted betwen clock cycles T2 and T3 during on board memory cycl es but it can be di sab1ed by a jum...

Page 49: ...iscussion above Furthermore the last eight groups are decoded as wri te on1y pOl ts by gati ng with the IOW strobe The complete list of I O port addresses is shown in table 4 1 The range of four contiguous addresses in each group is first shown If the device uses the AO or Al lines for direct addres sing of channels or registers within the circuit these are listed below the group range A15 A14 _e_...

Page 50: ...FDO FCF FCC FCF FCE FCD FCC N C N C N C Am9551 RS232 port Control Data Control same as FEF Data same as FEE Am9551 RS232 or TTY port Control Data Control same as FEB Data Same as FEA Am8253 counter time Mode control Counter 2 Counter 1 Counter 0 Keyboard return lines Keyboard scan lines Single step control Breakpoint register LED display 20th character left most 19th character 18th character 17th ...

Page 51: ...CB FCA FC9 FC8 FC7 FC4 FC7 FC6 FC5 FC4 FC3 FCO FC3 FC2 FCI FCO 12th character 11th character 10th character 9th character 8th character 7th character 6th character 5th character 4th character 3rd character 2nd character 1st character right most 4 7 ...

Page 52: ......

Page 53: ...e Mode 1 Input or out put li n conj unc t ion with strobed handshak ing signals Port A consists of 8 data lines in conjunc t ion wi th the upper four handshake 11 ines of port C Port B issimi 1ar but uses the lower four lines of port C for handshake All data 1ines are 1atched whether input or output Mode 2 Bidirectional data transfers on the ei ght 1i nes of port A controlled by the upper five mon...

Page 54: ... 1 Mode 1 C P rt C 7 1 Input 0 Output PortA 1 Input 0 Output L Mode Mode 0 01 Mode 1 1X Mode 2 1 Operation Control Word TABLE 5 2 Am8255A BIT SET RESET CONTROL WORD FORMAT L BIT SET RESET 1 SET 0 RESET PORT C BIT SELECT BIT 03 02 01 o 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 L 0 BIT SET RESET CONTROL WORD ...

Page 55: ...ode Contro1 Code fo11 o ied by one or two 8 bit synch characters followed by the same Control Command format illus trated above The format for the Syn chronous Mode Control Code is shown in table 5 6 If you wi sh to change the Monitor s initialization of the P6 USART after power up or if you intend to use the P5 USART the fo11 owi ng steps are re commended The format for the Control Command that f...

Page 56: ...6 5 4 3 2 1 0 Bit No I I I I I I I I r Lg l 10 10 11 Invalid Async mode 1 x Baud rate factor Async mode 16 x Baud rate factor Async mode 64 x Baud rate factor 5 bits per character 6 bits per character 7 bits per character 8 bits per character 5 4 o Parity disable 1 Parity enable o Odd parity 1 Even parity 00 Invalid 01 1 stop bit 10 1 1 stop bits 11 2 stop bits ...

Page 57: ...D is forced low o Normal operation ER 1 Resets all error flags in Status register PE OE FE RTS 1 FITS output is forced to 0 IR 1 Reset format EH 1 Enter HUNT mode TABLE 5 6 Am9551 SYNCHRONOUS MODE CONTROL CODE 0 Bit No 1 0 10 7 bits per character 11 8 bits per character 0 Parity disable 1 Parity enable Odd parity 1 Even parity SYNDET output SYNDET input 2 SYNC characters 1 SYNC character 5 5 ...

Page 58: ...F or FED CONTROL FEB or FE9 Am 9551 Am 9551 Serial I O Serial I O _ FEE or FEC DATA FEA or FEB P5 EDGE P6 CONNECTOR TABLE 5 8 Am9551 STATUS REGISTER 7 6 5 4 3 2 1 0 Bit No t lltltl II I I I I I I L DY I I L_______ PE Parity error Il 0 l _ __ _ DSR ...

Page 59: ... th the manner in which signals are output Mode a Interrupt on termi na1 count The output Ii 11 be 1nl tially low after the mode set operation After the count is loaded into the se1ected count regi ster the output will remain low and the counter will count When terminal count is Mode 1 reached the output will go high and remain high until the selected count register is reloaded with the mode Rel o...

Page 60: ...ill go high again If the count register is reloaded between output pulses the present period wi 11 not be affected but the subsequent peri od wi 11 reflect the new value The count will be inhibited while the gate input is low Reloading the counter register will restart coun ting beginning with the new number Mode 5 Hardware triggered strobe The counter will start count i ng after the ri sing edge ...

Page 61: ...ation f 1 a Read Load most sig nificant byte only r f a 1 Read Load least sig nificant byte only r f 1 1 Read Load least sig nificant byte first than most significant byte _ M2 MI Ma a 0 a Mode a a 0 1 Mode 1 X 1 a Mode 2 X 1 1 Mode 3 1 0 a Mode 4 _ 1 a 1 Mode 5 a Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades 5 9 ...

Page 62: ...TABLE 5 11 Am8253 CONTROL BYTE TO LATCH COUNT 07 06 05 04 03 02 01 DO _o f SCI SCO a a x x x x TABLE 5 12 Am8253 ADDRESSES COUNTERS o 2 FE4 I FE5 I FE6 STATUS READS Am 8253 Counter Timer FE7 CONTROL WR ITES ...

Page 63: ...STOP WAIT NMI NREQ BUSAK R W N S B W AS OS STO ST3 Delay output 9ns 9ns 9ns 9ns 9ns 9ns 9ns 9ns Setup input Ons Ons Ons Ons Ons 20ns 37ns Valid at least 35ns before r s ing edge of AS Addresses remain valid at least 7Ins after rising edge of OS Output valid within 66ns after falling edge of OS Input must be valid at least 93ns before falling edge of T3 It must remain valid until rising edge of OS ...

Page 64: ......

Page 65: ...51 81 Q 71 113 q 50 2 52 82 R 72 114 r 51 3 53 83 S 73 115 s 52 4 54 84 T 74 116 t 53 5 55 85 U 75 117 u 54 6 56 86 V 76 118 v 55 7 57 87 W 77 119 w 56 8 58 88 X 78 120 x 57 9 59 89 y 79 121 y 58 SA 90 Z 7A 122 z 59 5B 91 7B 123 60 5C 92 7C 124 I 61 5D 93 7D 125 62 5E 94 7E 126 63 SF 95 7F 127 DEL ex o 1 2 3 4 5 6 7 8 9 A B C D E F o 1 2 3 4 5 6 7 8 9 A B C D E F Hex Dec Char H 00 0 NUL 2 01 1 SOH...

Page 66: ......

Page 67: ...a purchase order is required Repackage the board in the orig inal packing material or an equivalent substitute and enclose in a corrugated carton suitable for shipping Seal the shipping carton securely mark it FRAGILE and address to Advanced Micro Computers Service Manager OEM Products 3340 Scott Boulevard Santa Clara California 95051 TELEPHONE 408 988 7777 TOLL FREE 800 672 3548 California 800 53...

Page 68: ... I I Figure C 1 Component Location Diagram ...

Page 69: ...1 _ RFSH SHT 2 P2 3 Ii 4 E ST STi ST2 ST 3 SHT6 4 5 5 83048 A7 i52 601 DIS A6 D AS g U50 14 011 SHT 7 A2 O A I 09 AO OB T R LS32 U68 2 r j c clliJBUSAK r o N G Iji SHT 4 5 HT 4 S __ 7 i R T SHT 6 6 6 19 E I JI2B7 I BG B S 16 B4 L T i 7 B3 L t l I T B 7 7 P30 AOIS 8t 0 5LS373 AOI4 781 n 4 I 0 3 U49 AOII 4g AOIl3 I 06 gi I 07 5V 10 152A3S244 2Y3 S V 17 2A4 i 2Y4 3 Lr ASp 2 9 t 2 _lIAI J1 I YI 1 8 _ ...

Page 70: ...T I 4 5 6 ARf U69 SHT I RFSH I SHT 1 6 7 MREQ I L AIS 14 B B 6 G 3 G2 GI Y7 25 LS 138 Y6 L 5HT I U63 2 6 7 AI4 3 C lL AI3 2 Y3K I A YZ 13 SK JI Kl A 12 Y I 14 4K I 4 K SHT vfl5 IS QlK lK_ I l I 1 IO Nn i 1Uo RlAi PARTSI IST lMLUSOTHEA MSESPECIFfED NO Adwnced MicroComputers DlIIEfGlONS ARf IN INCHES A A TOI ERANCESAAI FRACTlONS DECIMALS ANG1 S xx xxx APPROVALS DATE SCHEMATIC DIAGRAM MATEROAC IlIl Y...

Page 71: ... I C1I K 4K 2 A3 A4 D I I A7 II A r I All irK 20 c B A 7 7 6 5 4 4 950117 96 4016 3 L o _ _ A3 D B A Figure C 4 Am96 4016 Schematic Sheet 3 ...

Page 72: ...TED DATA 3 _ ntEA AAE 1ICHE8 TOLI fUoNCESAAI r 1 SCHEMATIC DIAGRAM 1s9 50oilIl7 1996 6 i440ioli66 _ t t r 8000 ION BOARD 1 1 1 _ 4 1489 3 I Ps 14 DATA TERMINAL READY UI2 1488 3 21JI3 P5 11 DATA SET READY 1459 E 4 P5 7 REQUEST TO SEND UI2 5 J13 PS 9 CLEAR TO SEND 1488 U 13 B RECEIVED DATA 9 10 10 TRANSMITTED DATA 8 UI2 CHASSIS GND GN D S 2 GN D 5 RTSp 2_3 TXD pi9 4 OTR 17 CT S 1 TXRDY L TXE IN C RX...

Page 73: ... Y3 12 Y41 6 C5 Y5 10 Y6 Y 7 7 7 7 _ __ 1 I dA 25LSI38 Y 1 15 1 111 1_1_1_ _L _O _4 I U 5 I l J GI Y4j 1 1 U69 Y5 5 G2B Yl 9 4 G2A Y7 l L15L5I38 Irffj U33 6 Gl P f S G28 I r 4 G2A III III L SISg J I H 2 3IB 1Y3 L f 1 l l2 IA 1 Y 2 U66 IYI 5 RD H I IG 1Y ili 4 C 4 T _ _ 7 L lWR I l l f_A0 l 21PA 1 8 i C I I 4 3 7 I D 3 1 21 f I 3 C71 10 L l_7I2 I D 4 I 30 D 4 L l 105 2 Db 1 1DC _11 l l l 4_ _ 2 D66...

Page 74: ...R E _____ 1 1 0 T 1 1 I Sl rS PFD4 I 7 I V 120 sv t 1 1 aB7 SHT 1 3 S I All 12 84 U2B lSHT 1 2 3 25LS2521 SHT 1 2 7 _ _ 3 OUT IO t 34 lH0J3 r elI E S t l1 H7A7 ID9 OI 1 15A6 1010 7 02 c 2 6 13 1 A S 1011 0325L c 13 Q3t c 1 l o SHT 3 7 1012 14 3 DO 4 5 U 17 QQS4 12E E 3 1 1013 Ac g I Hg r _ i4 kr ClK CLR _ _ I q to 1 RP4 LS0 0 6 4 sv N v I IU55 B JI 17K INC U70 SW 1 H A rSWITCH 7 NO _ RI PI 4_ J _ ...

Page 75: ...TI I O J t PR 12 D U53 Q 574 I LS08 c Q 2 54 3 RDy SHT I CL yl3 8 I 5V J 1C53l U l C21 2 C25 C27 CR3 22 r 1 Cl C l7SIA _ Jr _ l _ _ c 1 79 S 1c54 I LS04 b U69 J m eicJA IDIO i3AZ SHT I DII 4 A 3 6 1 01 A4 IDI E A IDI J ID c 1 5V 2G IG 5V IC3 R2 I 5HT5JIOADR I1C2 IyI 7 _ _ IV j5 V 1 5V J2 k US2 680 I RPo LSI4 2C3 S253 1 9 4 _7K _ _ l n o _ I II m 2Yr9 _ I R IC J WAI O U70 J92CIO 2 2K B A 8 _ _ _ _ ...

Page 76: ...cations Department 3340 Scott Boulevard Santa Clara CA 95051 TITLE Am96 4016 AmZ8000 EVALUATION BOARD USER S MANUAL PUBLICATION NO 0068013 1 g COMMENTS Describe errors suggested additions or deletions and include page numbers letq 1 From Name Company Address Position ...

Page 77: ...ADVANCED MICRO COMPUTERS 3340 Scott Boulevard Santa Clara California 95051 Distributed by Advanced Micro Devices ...