Advantech DSPC-8682, Hardware Manual

Page 1: ...Page 1 of 47 DSPC 8682 Octal TMS320C6678 DSP PCI E FLCard H W Manual Author Status Version 1 0 Document ID Location ...

Page 2: ...20C6678 BLOCK DIAGRAM 24 2 9 MEMORY DDR3 24 2 10 SRIO INTERFACE 24 2 11 PCI E INTERFACE 25 2 12 ETHERNET MAC 26 2 13 HYPERLINK INTERFACE 27 2 14 FGPA XC3S200AN 28 2 15 LEDS 30 3 IO CONNECTOR 32 3 1 CONNECTOR OVERVIEW 32 3 2 THE PEX8748 BCM5482S AND CPS1616 BOUNDARY SCAN CONNECTOR 33 3 3 TMS320C6678 BOUNDARY SCAN CONNECTOR 34 3 4 60 PINS DSP EMULATOR CONNECTOR 34 3 5 RJ45 LAN CONNECTOR 37 3 6 XILIN...

Page 3: ...78 BLOCK DIAGRAM 24 FIGURE12 SERIAL RAPIDIO RING 25 FIGURE13 PCIE INTERCONNECTION 26 FIGURE14 LAN INTERCONNECTION 27 FIGURE15 HYPERLINK CONNECTION 28 FIGURE16 FPGA CONNECTION 29 FIGURE17 TOP SIDE LED LOCATION 30 FIGURE18 CONNECTOR OVERVIEW 32 FIGURE19 CN1 BOUNDARY SCAN FOR PEX748 BCM5482S AND CPS1616 33 FIGURE20 CN2 THE BOUNDARY SCAN FOR THE DSP FARM 34 FIGURE21 CN3 TI 60 PIN EMULATION CONNECTOR 3...

Page 4: ...Page 4 of 47 FIGURE31 THE SW1 SCHEMATIC 42 FIGURE32 THE SW2 SCHEMATIC 44 FIGURE33 DSPC 8682 TOP SIDE 46 FIGURE34 DSPC 8682 FRONT SIDE 46 FIGURE 35 DSPC 8682 BOTTOM SIDE 47 ...

Page 5: ...TABLE5 PCI E SWITCH LED 30 TABLE6 FPGA LED 30 TABLE7 CN1 PIN ASSIGNMENT 33 TABLE 8 CN2 PIN ASSIGNMENT 34 TABLE 9 CN3 DSP EMULATOR PIN ASSIGNMENTS 36 TABLE10 CN4 PIN ASSIGNMENT 38 TABLE11 CN5 PIN ASSIGNMENT 38 TABLE12 CN6 PIN ASSIGNMENT 39 TABLE13 CN7 PIN ASSIGNMENT 40 TABLE14 CN8 PIN ASSIGNMENT 41 TABLE15 THE SW1 SETTING TABLE 43 TABLE16 THE SW2 SETTING TABLE 45 ...

Page 6: ...ist for detail Revision PCB SN PCB Rev Memory X 19C2868200 A101 1 Samsung 2G bits X 19C2868201 01 A102 1 Micron 4G bits Rev 05 19C2868201 01 A102 1 Samsung 4G bits Refer to blow picture to see the PCB SN Octal TMS320C6678 DSP PCI E FL Card contains very delicate integrated circuit chips In order to protect Octal TMS320C6678 DSP PCI E FL Card from static electricity you should follow some precautio...

Page 7: ...wnstream port PCI E GEN2x2 4 port to eight DSPs Ethernet PHY BCM5482S Support 10 100 1000 Mb s with 1000BASE T interface I O Expansion Standard PCI E x8 golden finger I O connector CN1 The PEX8748 BCM5482S and CPS1616 boundary scan connector CN2 The DSP Boundary Scan connector CN3 TI 60 pins DSP emulator connector CN4 RJ45 connectors for LANs CN5 FPGA JTAG connector CN6 DC 12V ATX power connector ...

Page 8: ...ot code and the initializations for the first boot while the card power on and then branch to PCI E interface for the second boot by the HOST computer One piece of 128kbit SPI EEPROM is attached to PCI E switch PEX8748 for specific port configurations One piece of 64kbit I2C EEPROM is attached to SRIO switch CPS1616 for port s routing table configurations Power Requirement 12V and 3 3V from PCI E ...

Page 9: ...ock DSP1 Block DSP7 Block DSP6 Block Hyperlink Hyperlink Hyperlink Hyperlink TMS320C6678 TMS320C6678 TMS320C6678 TMS320C6678 TMS320C6678 TMS320C6678 TMS320C6678 SGMII SRIOx1 SGMII SRIOx1 SRIOx1 SGMII SGMII SRIOx1 Switch 21x21mm CPS 1616 IDT SRIOx1 SGMII 1 SRIO Gen2 12Ports 48Lanes PEX8748 PLX TMS320C6678 DSP0 Block PCIEx8 Gen3 SGMII SRIOx1 SGMII SRIOx1 SRIOx2 SRIOx2 SRIOx2 SRIOx2 SRIOx2 SRIOx2 SRI...

Page 10: ...2 PCI E card Placement Below figure shows main components on DSPC 8682 It s only for reference if user needs to learn specific DSP or want to find a key chip on the card during developing Figure 2 DSPC 8682 PCI E card Placement ...

Page 11: ... 3A 0 75V Adjustable Core 0 9V 1 1V 10A VCC0P75 1 0V 8A DSP6 VID VCC0P75 VID Adjustable Core 0 9V 1 1V 10A DSP1 1 5V 1 3A 1 8V 0 416A 1 0V 8A Adjustable Core 0 9V 1 1V 10A 0 75V DVDD1P8 VCC1P0 VCC1P5 UCD74110 DDR3 1 UCD9244 SmartReflex PMbus V4 V2 V3 V1 4 4 DSP6_VartibleCore_1 0V DSP1_VartibleCore_1 0V DSP0_VartibleCore_1 0V 4 4 DSP7_VartibleCore_1 0V PWM PWM DSP0 TMS320C6678 PWM PWM PMbus_CLK PMb...

Page 12: ...re 0 9V 1 1V 10A 1 0V 8A 1 8V 0 416A 1 5V 1 3A 0 75V DDR4 PMbus SmartReflex UCD9244 2 V3 V2 V4 4 4 V1 DSP4_VartibleCore_1 0V DSP2_VartibleCore_1 0V DSP5_VartibleCore_1 0V 4 4 DSP3_VartibleCore_1 0V PWM PWM DSP4 PMbus_Cntrl PMbus_Alert PMbus_CLK PWM PWM GPIO_power_good 1 8V 0 416A 1 5V 1 3A 0 75V PMbus_DATA Adjustable Core 0 9V 1 1V 10A 1 0V 8A 1 8V 0 416A 1 0V 8A 0 75V 1 5V 1 3A UCD74110 VID DDR4 ...

Page 13: ...75 VCC5 5V 1A EN_VCC5 EN PG Max Delivery Current 3A MP28253EL PG_VCC5 VCC3 MOSFET PG PG_VCC3 VCC12 EN PG_VCC1P2SB PG VCC1P2SB Max Delivery Current 1A EN APL5912KAC 1 2VSB 0 2A PG PG_DVDD1P8 EN_DVDD1P8 MP28253EL 1 8V 2A DVDD1P8 EN Max Delivery Current 3A APL5912KAC 3VSB 3VSB Max Delivery Current 34A EN_VCC0P9 0 9V 15A VT237 EN MP28253EL EN EN_VCC1V2 1 2V 1 1A MP28253EL 2 5V 1A Max Delivery Current ...

Page 14: ... power dissipations and utilizations of the key components For detailed number it is summarized in the following table Table1 DSPC 8682 Power Budget VCC12 load 12 3 A VCC3 3 load 1 351 A Total power consumption for EE Design 152 06W Total power consumption for Thermal Design 106 639W Power budget table please refer to below Table 1 DSPC 8682 Power Budget ...

Page 15: ... DVDD1P2_EN 5ms t 200ms VCC1P2 IDT1616 5ms t 200ms IDT1616 VCC0P9 EN_VCC0P9 CPS1432_SRIO_RST PEX8748 BCM5482S PEX8748 t 1ms PEX8748_PCIE_RST POWER_GOOD Delay 100ms 3 3V standby pow er 3VSB FPGA VCC1P5 EN_VCC1P5 VCC0P75 VCC2P5 EN_VCC2P5 5ms t 200ms 5ms t 200ms 5ms t 200ms CVDD_DSP UCD9244_EN VCC1P0_1 EN_VCC1P0_1 DVDD1P8 EN_DVDD1P8 1V2SB 1 2VSB TMS320C6678 TMS320C6678 TMS320C6678 VCC3 EN_VCC3 BCM548...

Page 16: ...tribution on DSPC 8682 PCIe card Figure 7 Power Distribution on DSPC 8682 PCI E Card 3 3V 0 021A 1 2V 0 069A FPGA XC3S200AN 1 8V 0 021A 1V 0 84A VDDS Analog power for SerDes and Rx 3 3V 0 015A VCC3_1616 1 2V 0 46A VDDT Analog power for TX pairs CPS1616 PEX8748 1 8V 0 98A 0 9V 14 03A 1 2V 0 29A BCM5482S 1 8V 0 189A VDD3 VDDS VDDT 2 5V 0 082A DVDD1P8 VCCINT VCCAUX and VCCO supplies to the FPGA can b...

Page 17: ...ference clocks ICS853S12I It s a PCI E GEN3 clock buffer and provides nine reference clocks to the PCI E switch and support PCI E clock for DSP IDT_83PN156DKI It s a programmable LVPECL oscillator generator with 25 0MHz crystal It offer 156 25MHz by LVPECL level and transfer to CML level for SRIO switch by divider resistor CDCLVD110A It s a 1 10 LVDS clock buffer There are four clock buffers which...

Page 18: ..._DDR_CLKP DSP7_DDR_CLKN 166 67MHz TI_CDCLVD110ARHBR U19 DSP7 DSP0_CORE_CLKP DSP0_CORE_CLKN 100 00MHz TI_CDCLVD110ARHBR U23 DSP0 DSP1_CORE_CLKP DSP1_CORE_CLKN 100 00MHz TI_CDCLVD110ARHBR U23 DSP1 DSP2_CORE_CLKP DSP2_CORE_CLKN 100 00MHz TI_CDCLVD110ARHBR U23 DSP2 DSP3_CORE_CLKP DSP3_CORE_CLKN 100 00MHz TI_CDCLVD110ARHBR U23 DSP3 DSP4_CORE_CLKP DSP4_CORE_CLKN 100 00MHz TI_CDCLVD110ARHBR U23 DSP4 DSP5...

Page 19: ... 00MHz TI_CDCLVD110ARHBR U33 DSP3 DSP4_MCM_CLKP DSP4_MCM_CLKN 250 00MHz TI_CDCLVD110ARHBR U33 DSP4 DSP5_MCM_CLKP DSP5_MCM_CLKN 250 00MHz TI_CDCLVD110ARHBR U33 DSP5 DSP6_MCM_CLKP DSP6_MCM_CLKN 250 00MHz TI_CDCLVD110ARHBR U33 DSP6 DSP7_MCM_CLKP DSP7_MCM_CLKN 250 00MHz TI_CDCLVD110ARHBR U33 DSP7 ICS583_PCIE_REF_CLKP0 ICS583_PCIE_REF_CLKN0 100 00MHz IDT_ICS853S12AKI U34 DSP0 ICS583_PCIE_REF_CLKP1 ICS5...

Page 20: ...N156_SRIO_QN 83PN156_SRIO_QP 156 25MHz Oscillator 80HCPS1616RMI U10 Table 3 Clock Domains 250Mhz Diff 62005_CLK_SSP_CS0 62005_CLK_SSP_CLK 62005_CLK_SSP_MOSI 62005_CLK_SSP_MISO Control X TAL 25Mhz 100Mhz Diff SRIO_SGMI_CLKP N TMS320C6678 DSP 0 7 MCM_CLKP N CORE_CLKP N DSPn_SRIOSGMII_CLKP N 250Mhz Diff 250Mhz Diff 100Mhz Diff 166 67Mhz Diff Clock Diagram 250Mhz Diff U0 CDCE62005 U4 U3 U2 U1 EN3 TI C...

Page 21: ..._P N 100Mhz Diff Divider resistor LVPECL LVDS HCSL DSP2_PCIE_REF_CLKP N_LVDS DSP1_PCIE_REF_CLKP N_LVDS DSP0_PCIE_REF_CLKP N_LVDS DSP3_PCIE_REF_CLKP N_LVDS DSP7_PCIE_REF_CLKP N_LVDS DSP6_PCIE_REF_CLKP N_LVDS DSP5_PCIE_REF_CLKP N_LVDS DSP4_PCIE_REF_CLKP N_LVDS RC Transfer PEX8748_REF_CLKP N_LVDS DSP7_PCIE_REF_CLKP N DSP6_PCIE_REF_CLKP N DSP5_PCIE_REF_CLKP N DSP4_PCIE_REF_CLKP N PLX PEX8748 ...

Page 22: ... of BCM5482s the PHY chip CPS1616_RST of CPS 1616 SRIO switch and DSP 0 7 _RESET on eight DSP chips To wait for 5mS the FPGA de assert the DSP_POR to eight DSPs To wait for 5mS the FPAG de assert the DSP_RESETFULLz to eight DSPs During DSP_RESETFULLz de asserted the DSP straps the boot configurations on its own GPIO pins driven by the FPAG 1ms later after DSP_RESETFULLz de asserted the FPGA will s...

Page 23: ...describes the reset timings related to DSP power rails CVDD CVDD1 DVDD15 and DVDD18 reference clocks core clock and DDR3 clock and three reset events RESETz PORz and RESETFULLz User can refer to TMS320C6678 Data Manual on TI webpage for the details Figure10 The DSP Reset Sequence on DSPC 8682 ...

Page 24: ...r 4G bit 256M x 16 DDR3 devices via DDR interface 2 10 SRIO interface For SRIO connection It s has two kind of topology to link The one DSPC 8682 adopts a ring topology to chain eight DSPs by one lane SRIO interface One SRIO lane is connected to previous DSP while another lane is connected to next DSP on DSPC 8682 e g the DSP 7 connects the DSP 0 with x1 SRIO port and connect the DSP 6 with anothe...

Page 25: ...GT s Lane x 48 SerDes x 2 full duplex Below table describes the port mapping of PEX8748 on DSPC 8682 while below figure describes the PCI E interconnection on DSPC 8682 Port Function 0 Connects to Host computer Root Complex by PCI E X8 1 Connects to DSP0 through PCI E X2 interface 2 Connects to DSP1 through PCI E X2 interface 8 Connects to DSP2 through PCI E X2 interface 9 Connects to DSP3 through...

Page 26: ...P while another lane is connected to next DSP on DSPC 8682 e g the DSP 0 connects the DSP 1 with x1 SGMII port and connect the DSP 2 with another x1 SGMII port On DSPC 8682 a daisy chain for LAN connections in implemented whereas the LAN port is connected to DSP 0 via a PHY BCM5482s to provide 1000BASE T Gigabit Ethernet feature With Ethernet PHY BCM5482S it supports Ethernet 10 100 1000M bit s wi...

Page 27: ...er lane for data transactions This HyperLink interface on the TMS320C6678 is used to exchange data between two DSPs with low latency for the specific process accelerations on DSPC 8682 PCIE card There are four lane SerDes interface designed to operate up to 12 5Gbps per lane The links of the HyperLink bus on DSPC 8682 are connected of the DSP 0 and the DSP 7as well as the DSP 1 and DSP 6 DSP 2 and...

Page 28: ...s and reset events for DPS farm With the programmed FPGA on DSPC 8682 below functions are provided DSP boot mode setting Power sequences control Enabling Disabling the device power to meet the power sequence requirement Reset methodology control Asserting De asserting RESET signals to each chip respectively Configure the clock generator Other control functions Below figure describes the FPGA conne...

Page 29: ..._SI1 0 3 CLK_Buf_CK 0 3 DVDD_1P8 VCC0P9 VCC1P2 VCC1P5 VCC1P0 VCC3 VCC2P5 Temp_DSP4_7 Hardware Montor Temp_DSP0_3 EN_VCC1P0_1 EN_VCC3 EN_VCC2P5 EN_DVDD1P8 EN_VCC0P9 EN_VCC1P2 PG_CVDD0_3 EN_VCC1P5 POR RESET RESETFULL HOUT BOOTCOMPLETE Control Sequences Power Configurations CLOCK FPGA_JTAG_TMS FPGA_JTAG_TDO FPGA_JTAG_TDI configurations Boot Device FPGA JTAG Control RESET DSP DSP Interrupts Control PH...

Page 30: ...rror D4 PEX8748 interrupt Table5 PCI E switch LED Some LEDs are near XC3S200AN Four LEDs are used for code debugging and one LED indicates that all power rails are good Details are shown as below Table6 LED Port SYSPG_D1 All power rails are good FPGA_LED1 Debug LED_1 FPGA_LED2 Debug LED_2 FPGA_LED3 Debug LED_4 FPGA_LED4 Debug LED_3 Table6 FPGA LED Some LEDs are built in RJ45 connector for RJ45 beh...

Page 31: ...Page 31 of 47 established The left side green LED present color when 100 BASE TX Link is established If left side LED is dark it means 10 BASE T link is established or no link is established ...

Page 32: ... facility test only CN3 TI 60 pins DSP emulator connector for software development CN4 RJ45 connectors for LANs 2 Giga Ethernet ports connected to DSP 0 and DSP 7 for networking applications CN5 FPGA JTAG connector for the FPGA debugging and new firmware updating CN6 DC 12V ATX power connector for increase the 12V input current CN7 FAN connector for the FAN attached on the heat sink CN8 FAN connec...

Page 33: ...connector Figure19 CN1 Boundary Scan for PEX748 BCM5482s and CPS1616 PIN Define PIN Define 1 TRSTn 2 JTAG_SW_CTRL 3 TDI 4 NC 5 TDO 6 GND 7 TMS 8 GND 9 TCK 10 GND Table7 CN1 Pin Assignment OUT CHAIN1_JTAG_SW_CTRL 98 C769 100pF 50V 0402 R788 68 5 CN1 PH_5x2V_S2 00mm 2 4 6 8 10 1 3 5 7 9 R134 1K 1 VCC3 OUT CHAIN1_JTAG_TDO 98 OUT CHAIN1_JTAG_TMS 106 OUT CHAIN1_JTAG_TCK 106 IN CHAIN1_JTAG_TDI 103 OUT C...

Page 34: ... TRSTn 2 JTAG_SW_CTRL 3 TDO 4 NC 5 TDI 6 GND 7 TMS 8 GND 9 TCK 10 GND Table 8 CN2 Pin Assignment 3 4 60 pins DSP emulator connector In this paragraph we introduce the 60 pin DSP emulator connector used for XDS562V2 CN3 60 pins DSP emulator connector CN2 PH_5x2V_S2 00mm 2 4 6 8 10 1 3 5 7 9 R126 1K 1 C1 100pF 50V 0402 R43 68 5 VCC3 OUT CONN40_TCK 106 IN CONN40_TDO 18 OUT CONN40_TDI 106 OUT JTAG_SW_...

Page 35: ...CK_L TRGRSTZ DSP0_EMU_15_R CONN60_TMS_1 8V DSP0_EMU_15 CONN60_TDI DSP0_EMU_12_R DSP0_EMU_08 DSP0_EMU_08_R DSP0_EMU_12 Remove terminal resistance R797 10 5 R90 10 5 R149 10 5 R163 4 7K R842 10 5 R875 10 5 R130 10 5 R120 NL 10K 1 R100 10 5 R864 10 5 R880 10 5 R135 10 5 R103 10 5 R898 10 5 R871 10 5 R876 10 5 R140 10 5 R44 10 5 R106 10 5 R111 100 1 R872 10 5 R885 10 5 R52 10 5 R141 10 5 R895 10 5 R87...

Page 36: ...3 GND EMU17 TRST GND 4 GND TDI EMU16 GND 5 GND EMU14 EMU15 GND 6 GND EMU12 EMU13 GND 7 GND TDO EMU11 GND 8 Reserve TVD TCLKRTN GND 9 GND EMU9 EMU10 GND 10 GND EMU7 EMU8 GND 11 GND EMU5 EMU6 GND 12 GND TCLK EMU4 GND 13 GND EMU2 EMU3 GND 14 GND EMU0 EMU1 GND 15 TGRST GND GND GND Table 9 CN3 DSP Emulator Pin Assignments Pin1 ...

Page 37: ...A4 A5 A6 A7 A8 A9 A10 B5 B1 B2 B3 B4 B7 B8 B9 B10 B6 B13 B14 B11 B12 BI 5482S_TRD1_1P 95 BI 5482S_TRD1_0P 95 BI 5482S_TRD1_0N 95 BI 5482S_TRD1_1N 95 5482S_RJ451_VCC VCC2P5 GND_SHIELD IN 5482S_LAN1_ACT 86 5482S_LAN1_ACT 5482S_LAN1_ACT_R R917 220 5 5482S_LAN1_LINK_R R1172 220 5 IN 5482S_LAN1_LINK 86 5482S_LAN1_LINK 5482S_LAN1_SPEED2_R R167 220 5 IN 5482S_LAN1_SPEED2 86 5482S_LAN1_SPEED2 IN 5482S_LAN...

Page 38: ...INX XC3S200AN JTAG interface In this paragraph we introduce the connector for Xilinx XC3S200AN JTAG interface CN5 XILINX XC3S200AN JTAG interface Figure26 CN5 the FPGA JTAG for firmware update PIN Define 1 VCC 2 GND 3 TCK 4 TDO 5 TDI 6 TMS Table11 CN5 Pin Assignment C78 0 1uF 16V CN5 PH_6x1V_2 54mm 1 2 3 4 5 6 3VSB FPGA_JTAG_TCK FPGA_JTAG_TDO FPGA_JTAG_TDI FPGA_JTAG_TMS ...

Page 39: ... 4 pin 12V ATX connector used to support 12V current rating for DSPC 8682 Figure27 CN6 12V connector PIN Define 1 VCC 2 VCC 3 VCC 4 GND 5 GND 6 GND Table12 CN6 Pin Assignment CN6 Characteristic ATX_3x2H_4 2mm 1 2 3 4 5 6 H1 H2 C663 10uF 16V VCC12_ATX C2531 10uF 16V C661 0 1uF 16V ...

Page 40: ... FAN connector CN7 FAN connector Figure28 CN7 FAN connector PIN Define 1 GND 2 VCC 3 Fan speed Table13 CN7 Pin Assignment FAN_SPEED1 B27 30_100MHz 3A CN7 WB_3V_2 0mm 1 2 3 R1472 27K 5 C668 0 1uF 16V FAN CNN1 D7 BAS32L 300mA 1 2 R1488 4 7K 1 R1446 10K 5 C2569 10uF 16V ...

Page 41: ... FAN connector CN8 FAN connector Figure29 CN8 FAN connector PIN Define 1 GND 2 VCC 3 Fan speed Table14 CN8 Pin Assignment FAN_SPEED2 B108 30_100MHz 3A CN8 WB_3V_2 0mm 1 2 3 R1464 27K 5 C2571 0 1uF 16V FAN CNN2 D6 BAS32L 300mA 1 2 R679 4 7K 1 R1463 10K 5 C2574 10uF 16V ...

Page 42: ...gure shows the position of the 4 bit sliding switch Figure30 The SW1 on DSPC 8682 PCIe Card Below figure shows the sliding switch circuit and notes the bit number for use Figure31 The SW1 Schematic DSP_BOOT_STRAP3 DSP_BOOT_STRAP0 DSP_BOOT_STRAP2 DSP_BOOT_STRAP1 R290 100 1 ON SW1 160_SW_8P_CHS 04TB 2_0 1 2 3 4 5 8 6 7 R170 10K 5 R171 10K 5 R289 100 1 R169 10K 5 R288 100 1 R168 10K 5 VCC3V3_FPGA R28...

Page 43: ...ation setting is as below SW1 bit1 Endian 0 Big Endian 1 Little Endian default The Boot interface of the DSP the setting is as below SW1 bit 4 2 000 None boot This mode is for the purpose of the development SW1 bit 4 2 001 I2C boot This mode is booting DSP from 0x51h of EEPROM and branch to the PCIE bus for the second boot default SW1 bit 4 2 010 PCIE Boot This mode is booting DSP from PCIE interf...

Page 44: ... to re flash EEPROM if need to change the setting from 2x to 1x Below figure shows the position of the 4 bit sliding switch Below figure shows the sliding switch circuit and notes the quadrant configuration QCFG number for use Figure32 The SW2 Schematic ON SW2 160_SW_8P_CHS 04TB 2_0 1 2 3 4 5 8 6 7 CPS1616_QCFG7 CPS1616_QCFG5 CPS1616_QCFG3 CPS1616_QCFG1 R870 0 5 R869 0 5 R99 0 5 R97 0 5 ...

Page 45: ...onfiguration Bit4 Bit3 Bit2 Bit1 Description QCF 1 QCF 3 QCF 5 QCF 7 0000 The SRIO ports of CPS1616 configure to 2x default QCF 1 QCF 3 QCF 5 QCF 7 1111 ON ON ON ON The SRIO ports of CPS1616 configure to 1x This setting need to re flash routing table from 2x to 1x Table16 The SW2 setting table ...

Page 46: ...Page 46 of 47 5 Mechanical Drawing Figure33 DSPC 8682 TOP side Figure34 DSPC 8682 Front Side ...

Page 47: ...Page 47 of 47 Figure 35 DSPC 8682 Bottom Side ...