Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
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PRELIMINARY
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO
MARCH 2005
REV. P1.0.6
GENERAL DESCRIPTION
The XRT86VL38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R
3
technology (Relayless,
Reconfigurable, Redundancy). The physical
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86VL38
provides protection from power failures and hot
swapping.
The XRT86VL38 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VL38 fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor,
Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
F
IGURE
1. XRT86VL38 8-
CHANNEL
DS1 (T1/E1/J1) F
RAMER
/LIU C
OMBO
Performance
Monitor
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
LIU &
Loopback
Control
DMA
Interface
Signaling &
Alarms
JTAG
WR
ALE_AS
RD
RDY_DTACK
µ
P
Select
A[14:0]
D[7:0]
Microprocessor
Interface
4
3
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Local PCM
Highway
ST-
BUS
2-Frame
Slip Buffer
Elastic Store
Tx Serial
Data In
Tx LIU
Interface
2-Frame
Slip Buffer
Elastic Store
Rx LIU
Interface
Rx Framer
Rx Serial
Data Out
RTIP
RRING
TTIP
TRING
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
XRT86VL38
1 of 8-channels
Tx Framer
LLB
LB
System (Terminal) Side
Line Side
1:1 Turns Ratio
1:2 Turns Ratio
Memory
Intel/Motorola µP
Configuration, Control &
Status Monitor
RxLOS
TxON
INT